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jannaujannau
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arm64: dts: apple: Move PCIe-GE nodes intro their own file
These are only used on the Mac Pro (M2 Ultra, 2023) so do not bloat all other DTBs. Signed-off-by: Janne Grunau <j@jannau.net>
1 parent 522ffc2 commit d51763c

4 files changed

Lines changed: 114 additions & 80 deletions

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‎arch/arm64/boot/dts/apple/t6022-j180d.dts‎

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/dts-v1/;
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#include "t6022.dtsi"
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#include "t6022-pcie-ge.dtsi"
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#include "t6022-jxxxd.dtsi"
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/ {

‎arch/arm64/boot/dts/apple/t6022-pcie-ge.dtsi‎

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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Include PCIe-GE nodes presen on both dies of T6022 (M2 Ultra) in the
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* Mac Pro (2023).
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*
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* Copyright The Asahi Linux Contributors
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*/
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#define DIE
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#define DIE_NO 0
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&die0 {
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#include "t602x-pcie-ge.dtsi"
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};
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#undef DIE
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#undef DIE_NO
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#define DIE _die1
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#define DIE_NO 1
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&die1 {
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#include "t602x-pcie-ge.dtsi"
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};
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#undef DIE
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#undef DIE_NO

‎arch/arm64/boot/dts/apple/t602x-dieX.dtsi‎

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@@ -671,83 +671,3 @@
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power-domains = <&DIE_NODE(ps_atc3_usb)>;
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status = "disabled";
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};
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DIE_NODE(pcie_ge): pcie@1680000000 {
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compatible = "apple,t6020-pcie-ge", "apple,t6020-pcie";
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device_type = "pci";
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reg = <0x16 0x80000000 0x0 0x1000000>, /* config */
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<0x16 0x91000000 0x0 0x4000>, /* rc */
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<0x16 0x94008000 0x0 0x4000>, /* port0 */
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<0x16 0x9e01c000 0x0 0x4000>, /* phy0 */
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<0x16 0x9401c000 0x0 0x1000>; /* ltssm0 */
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reg-names = "config", "rc", "port0", "phy0", "ltssm0";
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ DIE_NO 1356 IRQ_TYPE_LEVEL_HIGH>;
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msi-controller;
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msi-parent = <&DIE_NODE(pcie_ge)>;
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msi-ranges = <&aic AIC_IRQ DIE_NO 1672 IRQ_TYPE_EDGE_RISING 128>;
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iommu-map = <0x000 &DIE_NODE(pcie_ge_dart) 0 0>,
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<0x100 &DIE_NODE(pcie_ge_dart) 1 1>,
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<0x200 &DIE_NODE(pcie_ge_dart) 2 2>,
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<0x300 &DIE_NODE(pcie_ge_dart) 3 3>,
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<0x400 &DIE_NODE(pcie_ge_dart) 4 4>,
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<0x500 &DIE_NODE(pcie_ge_dart) 5 5>,
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<0x600 &DIE_NODE(pcie_ge_dart) 6 6>,
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<0x700 &DIE_NODE(pcie_ge_dart) 7 7>,
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<0x800 &DIE_NODE(pcie_ge_dart) 8 8>,
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<0x900 &DIE_NODE(pcie_ge_dart) 9 9>,
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<0xa00 &DIE_NODE(pcie_ge_dart) 10 10>,
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<0xb00 &DIE_NODE(pcie_ge_dart) 11 11>,
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<0xc00 &DIE_NODE(pcie_ge_dart) 12 12>,
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<0xd00 &DIE_NODE(pcie_ge_dart) 13 13>,
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<0xe00 &DIE_NODE(pcie_ge_dart) 14 14>;
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iommu-map-mask = <0xff00>;
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bus-range = <0 15>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>,
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<0x02000000 0x0 0x80000000 0x17 0x80000000 0x0 0x80000000>;
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power-domains = <&DIE_NODE(ps_apcie_ge_sys)>;
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pinctrl-0 = <&DIE_NODE(pcie_ge_pins)>;
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pinctrl-names = "default";
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dma-coherent;
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status = "disabled";
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DIE_NODE(port_ge00): pci@0,0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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reset-gpios = <&DIE_NODE(pinctrl_ap) 9 GPIO_ACTIVE_LOW>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &DIE_NODE(port_ge00) 0 0 0 0>,
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<0 0 0 2 &DIE_NODE(port_ge00) 0 0 0 1>,
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<0 0 0 3 &DIE_NODE(port_ge00) 0 0 0 2>,
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<0 0 0 4 &DIE_NODE(port_ge00) 0 0 0 3>;
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};
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};
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DIE_NODE(pcie_ge_dart): iommu@1694000000 {
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compatible = "apple,t6020-dart", "apple,t8110-dart";
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reg = <0x16 0x94000000 0x0 0x4000>;
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#iommu-cells = <1>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ DIE_NO 1357 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&DIE_NODE(ps_apcie_ge_sys)>;
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status = "disabled";
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};
753-

‎arch/arm64/boot/dts/apple/t602x-pcie-ge.dtsi‎

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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* PCIe-GE Nodes present on both dies of a T6022 (M2 Ultra) and M2 Pro/Max but
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* only used on T6022 in the Mac Pro (2023).
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*
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* Copyright The Asahi Linux Contributors
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*/
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DIE_NODE(pcie_ge): pcie@1680000000 {
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compatible = "apple,t6020-pcie-ge", "apple,t6020-pcie";
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device_type = "pci";
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reg = <0x16 0x80000000 0x0 0x1000000>, /* config */
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<0x16 0x91000000 0x0 0x4000>, /* rc */
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<0x16 0x94008000 0x0 0x4000>, /* port0 */
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<0x16 0x9e01c000 0x0 0x4000>, /* phy0 */
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<0x16 0x9401c000 0x0 0x1000>; /* ltssm0 */
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reg-names = "config", "rc", "port0", "phy0", "ltssm0";
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ DIE_NO 1356 IRQ_TYPE_LEVEL_HIGH>;
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msi-controller;
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msi-parent = <&DIE_NODE(pcie_ge)>;
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msi-ranges = <&aic AIC_IRQ DIE_NO 1672 IRQ_TYPE_EDGE_RISING 128>;
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iommu-map = <0x000 &DIE_NODE(pcie_ge_dart) 0 0>,
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<0x100 &DIE_NODE(pcie_ge_dart) 1 1>,
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<0x200 &DIE_NODE(pcie_ge_dart) 2 2>,
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<0x300 &DIE_NODE(pcie_ge_dart) 3 3>,
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<0x400 &DIE_NODE(pcie_ge_dart) 4 4>,
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<0x500 &DIE_NODE(pcie_ge_dart) 5 5>,
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<0x600 &DIE_NODE(pcie_ge_dart) 6 6>,
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<0x700 &DIE_NODE(pcie_ge_dart) 7 7>,
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<0x800 &DIE_NODE(pcie_ge_dart) 8 8>,
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<0x900 &DIE_NODE(pcie_ge_dart) 9 9>,
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<0xa00 &DIE_NODE(pcie_ge_dart) 10 10>,
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<0xb00 &DIE_NODE(pcie_ge_dart) 11 11>,
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<0xc00 &DIE_NODE(pcie_ge_dart) 12 12>,
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<0xd00 &DIE_NODE(pcie_ge_dart) 13 13>,
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<0xe00 &DIE_NODE(pcie_ge_dart) 14 14>;
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iommu-map-mask = <0xff00>;
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bus-range = <0 15>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>,
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<0x02000000 0x0 0x80000000 0x17 0x80000000 0x0 0x80000000>;
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power-domains = <&DIE_NODE(ps_apcie_ge_sys)>;
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pinctrl-0 = <&DIE_NODE(pcie_ge_pins)>;
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pinctrl-names = "default";
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dma-coherent;
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status = "disabled";
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DIE_NODE(port_ge00): pci@0,0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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reset-gpios = <&DIE_NODE(pinctrl_ap) 9 GPIO_ACTIVE_LOW>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &DIE_NODE(port_ge00) 0 0 0 0>,
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<0 0 0 2 &DIE_NODE(port_ge00) 0 0 0 1>,
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<0 0 0 3 &DIE_NODE(port_ge00) 0 0 0 2>,
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<0 0 0 4 &DIE_NODE(port_ge00) 0 0 0 3>;
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};
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};
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DIE_NODE(pcie_ge_dart): iommu@1694000000 {
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compatible = "apple,t6020-dart", "apple,t8110-dart";
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reg = <0x16 0x94000000 0x0 0x4000>;
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#iommu-cells = <1>;
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interrupt-parent = <&aic>;
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interrupts = <AIC_IRQ DIE_NO 1357 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&DIE_NODE(ps_apcie_ge_sys)>;
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status = "disabled";
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};

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