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martijndegouwbroonie
martijndegouw
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broonie
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regulator: pca9450: Add support for setting debounce settings
Make the different debounce timers configurable from the devicetree. Depending on the board design, these have to be set different than the default register values. Signed-off-by: Martijn de Gouw <martijn.de.gouw@prodrive-technologies.com> Link: https://patch.msgid.link/20251117202215.1936139-2-martijn.de.gouw@prodrive-technologies.com Signed-off-by: Mark Brown <broonie@kernel.org>
1 parent 93218e3 commit d9d0be5

2 files changed

Lines changed: 171 additions & 19 deletions

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‎drivers/regulator/pca9450-regulator.c‎

Lines changed: 139 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1147,6 +1147,143 @@ static int pca9450_i2c_restart_handler(struct sys_off_data *data)
11471147
return 0;
11481148
}
11491149

1150+
static int pca9450_of_init(struct pca9450 *pca9450)
1151+
{
1152+
struct i2c_client *i2c = container_of(pca9450->dev, struct i2c_client, dev);
1153+
int ret;
1154+
unsigned int val;
1155+
unsigned int reset_ctrl;
1156+
unsigned int rstb_deb_ctrl;
1157+
unsigned int t_on_deb, t_off_deb;
1158+
unsigned int t_on_step, t_off_step;
1159+
unsigned int t_restart;
1160+
1161+
if (of_property_read_bool(i2c->dev.of_node, "nxp,wdog_b-warm-reset"))
1162+
reset_ctrl = WDOG_B_CFG_WARM;
1163+
else
1164+
reset_ctrl = WDOG_B_CFG_COLD_LDO12;
1165+
1166+
/* Set reset behavior on assertion of WDOG_B signal */
1167+
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_RESET_CTRL,
1168+
WDOG_B_CFG_MASK, reset_ctrl);
1169+
if (ret)
1170+
return dev_err_probe(&i2c->dev, ret, "Failed to set WDOG_B reset behavior\n");
1171+
1172+
ret = of_property_read_u32(i2c->dev.of_node, "npx,pmic-rst-b-debounce-ms", &val);
1173+
if (ret == -EINVAL)
1174+
rstb_deb_ctrl = T_PMIC_RST_DEB_50MS;
1175+
else if (ret)
1176+
return ret;
1177+
else {
1178+
switch (val) {
1179+
case 10: rstb_deb_ctrl = T_PMIC_RST_DEB_10MS; break;
1180+
case 50: rstb_deb_ctrl = T_PMIC_RST_DEB_50MS; break;
1181+
case 100: rstb_deb_ctrl = T_PMIC_RST_DEB_100MS; break;
1182+
case 500: rstb_deb_ctrl = T_PMIC_RST_DEB_500MS; break;
1183+
case 1000: rstb_deb_ctrl = T_PMIC_RST_DEB_1S; break;
1184+
case 2000: rstb_deb_ctrl = T_PMIC_RST_DEB_2S; break;
1185+
case 4000: rstb_deb_ctrl = T_PMIC_RST_DEB_4S; break;
1186+
case 8000: rstb_deb_ctrl = T_PMIC_RST_DEB_8S; break;
1187+
default: return -EINVAL;
1188+
}
1189+
}
1190+
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_RESET_CTRL,
1191+
T_PMIC_RST_DEB_MASK, rstb_deb_ctrl);
1192+
if (ret)
1193+
return dev_err_probe(&i2c->dev, ret, "Failed to set PMIC_RST_B debounce time\n");
1194+
1195+
ret = of_property_read_u32(i2c->dev.of_node, "nxp,pmic-on-req-on-debounce-us", &val);
1196+
if (ret == -EINVAL)
1197+
t_on_deb = T_ON_DEB_20MS;
1198+
else if (ret)
1199+
return ret;
1200+
else {
1201+
switch (val) {
1202+
case 120: t_on_deb = T_ON_DEB_120US; break;
1203+
case 20000: t_on_deb = T_ON_DEB_20MS; break;
1204+
case 100000: t_on_deb = T_ON_DEB_100MS; break;
1205+
case 750000: t_on_deb = T_ON_DEB_750MS; break;
1206+
default: return -EINVAL;
1207+
}
1208+
}
1209+
1210+
ret = of_property_read_u32(i2c->dev.of_node, "nxp,pmic-on-req-off-debounce-us", &val);
1211+
if (ret == -EINVAL)
1212+
t_off_deb = T_OFF_DEB_120US;
1213+
else if (ret)
1214+
return ret;
1215+
else {
1216+
switch (val) {
1217+
case 120: t_off_deb = T_OFF_DEB_120US; break;
1218+
case 2000: t_off_deb = T_OFF_DEB_2MS; break;
1219+
default: return -EINVAL;
1220+
}
1221+
}
1222+
1223+
ret = of_property_read_u32(i2c->dev.of_node, "nxp,power-on-step-ms", &val);
1224+
if (ret == -EINVAL)
1225+
t_on_step = T_ON_STEP_2MS;
1226+
else if (ret)
1227+
return ret;
1228+
else {
1229+
switch (val) {
1230+
case 1: t_on_step = T_ON_STEP_1MS; break;
1231+
case 2: t_on_step = T_ON_STEP_2MS; break;
1232+
case 4: t_on_step = T_ON_STEP_4MS; break;
1233+
case 8: t_on_step = T_ON_STEP_8MS; break;
1234+
default: return -EINVAL;
1235+
}
1236+
}
1237+
1238+
ret = of_property_read_u32(i2c->dev.of_node, "nxp,power-down-step-ms", &val);
1239+
if (ret == -EINVAL)
1240+
t_off_step = T_OFF_STEP_8MS;
1241+
else if (ret)
1242+
return ret;
1243+
else {
1244+
switch (val) {
1245+
case 2: t_off_step = T_OFF_STEP_2MS; break;
1246+
case 4: t_off_step = T_OFF_STEP_4MS; break;
1247+
case 8: t_off_step = T_OFF_STEP_8MS; break;
1248+
case 16: t_off_step = T_OFF_STEP_16MS; break;
1249+
default: return -EINVAL;
1250+
}
1251+
}
1252+
1253+
ret = of_property_read_u32(i2c->dev.of_node, "nxp,restart-ms", &val);
1254+
if (ret == -EINVAL)
1255+
t_restart = T_RESTART_250MS;
1256+
else if (ret)
1257+
return ret;
1258+
else {
1259+
switch (val) {
1260+
case 250: t_restart = T_RESTART_250MS; break;
1261+
case 500: t_restart = T_RESTART_500MS; break;
1262+
default: return -EINVAL;
1263+
}
1264+
}
1265+
1266+
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_PWRCTRL,
1267+
T_ON_DEB_MASK | T_OFF_DEB_MASK | T_ON_STEP_MASK |
1268+
T_OFF_STEP_MASK | T_RESTART_MASK,
1269+
t_on_deb | t_off_deb | t_on_step |
1270+
t_off_step | t_restart);
1271+
if (ret)
1272+
return dev_err_probe(&i2c->dev, ret,
1273+
"Failed to set PWR_CTRL debounce configuration\n");
1274+
1275+
if (of_property_read_bool(i2c->dev.of_node, "nxp,i2c-lt-enable")) {
1276+
/* Enable I2C Level Translator */
1277+
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_CONFIG2,
1278+
I2C_LT_MASK, I2C_LT_ON_STANDBY_RUN);
1279+
if (ret)
1280+
return dev_err_probe(&i2c->dev, ret,
1281+
"Failed to enable I2C level translator\n");
1282+
}
1283+
1284+
return 0;
1285+
}
1286+
11501287
static int pca9450_i2c_probe(struct i2c_client *i2c)
11511288
{
11521289
enum pca9450_chip_type type = (unsigned int)(uintptr_t)
@@ -1156,7 +1293,6 @@ static int pca9450_i2c_probe(struct i2c_client *i2c)
11561293
struct regulator_dev *ldo5;
11571294
struct pca9450 *pca9450;
11581295
unsigned int device_id, i;
1159-
unsigned int reset_ctrl;
11601296
int ret;
11611297

11621298
pca9450 = devm_kzalloc(&i2c->dev, sizeof(struct pca9450), GFP_KERNEL);
@@ -1254,25 +1390,9 @@ static int pca9450_i2c_probe(struct i2c_client *i2c)
12541390
if (ret)
12551391
return dev_err_probe(&i2c->dev, ret, "Failed to clear PRESET_EN bit\n");
12561392

1257-
if (of_property_read_bool(i2c->dev.of_node, "nxp,wdog_b-warm-reset"))
1258-
reset_ctrl = WDOG_B_CFG_WARM;
1259-
else
1260-
reset_ctrl = WDOG_B_CFG_COLD_LDO12;
1261-
1262-
/* Set reset behavior on assertion of WDOG_B signal */
1263-
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_RESET_CTRL,
1264-
WDOG_B_CFG_MASK, reset_ctrl);
1393+
ret = pca9450_of_init(pca9450);
12651394
if (ret)
1266-
return dev_err_probe(&i2c->dev, ret, "Failed to set WDOG_B reset behavior\n");
1267-
1268-
if (of_property_read_bool(i2c->dev.of_node, "nxp,i2c-lt-enable")) {
1269-
/* Enable I2C Level Translator */
1270-
ret = regmap_update_bits(pca9450->regmap, PCA9450_REG_CONFIG2,
1271-
I2C_LT_MASK, I2C_LT_ON_STANDBY_RUN);
1272-
if (ret)
1273-
return dev_err_probe(&i2c->dev, ret,
1274-
"Failed to enable I2C level translator\n");
1275-
}
1395+
return dev_err_probe(&i2c->dev, ret, "Unable to parse OF data\n");
12761396

12771397
/*
12781398
* For LDO5 we need to be able to check the status of the SD_VSEL input in

‎include/linux/regulator/pca9450.h‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -223,12 +223,44 @@ enum {
223223
#define IRQ_THERM_105 0x02
224224
#define IRQ_THERM_125 0x01
225225

226+
/* PCA9450_REG_PWRCTRL bits */
227+
#define T_ON_DEB_MASK 0xC0
228+
#define T_ON_DEB_120US (0 << 6)
229+
#define T_ON_DEB_20MS (1 << 6)
230+
#define T_ON_DEB_100MS (2 << 6)
231+
#define T_ON_DEB_750MS (3 << 6)
232+
#define T_OFF_DEB_MASK 0x20
233+
#define T_OFF_DEB_120US (0 << 5)
234+
#define T_OFF_DEB_2MS (1 << 5)
235+
#define T_ON_STEP_MASK 0x18
236+
#define T_ON_STEP_1MS (0 << 3)
237+
#define T_ON_STEP_2MS (1 << 3)
238+
#define T_ON_STEP_4MS (2 << 3)
239+
#define T_ON_STEP_8MS (3 << 3)
240+
#define T_OFF_STEP_MASK 0x06
241+
#define T_OFF_STEP_2MS (0 << 1)
242+
#define T_OFF_STEP_4MS (1 << 1)
243+
#define T_OFF_STEP_8MS (2 << 1)
244+
#define T_OFF_STEP_16MS (3 << 1)
245+
#define T_RESTART_MASK 0x01
246+
#define T_RESTART_250MS 0
247+
#define T_RESTART_500MS 1
248+
226249
/* PCA9450_REG_RESET_CTRL bits */
227250
#define WDOG_B_CFG_MASK 0xC0
228251
#define WDOG_B_CFG_NONE 0x00
229252
#define WDOG_B_CFG_WARM 0x40
230253
#define WDOG_B_CFG_COLD_LDO12 0x80
231254
#define WDOG_B_CFG_COLD 0xC0
255+
#define T_PMIC_RST_DEB_MASK 0x07
256+
#define T_PMIC_RST_DEB_10MS 0x00
257+
#define T_PMIC_RST_DEB_50MS 0x01
258+
#define T_PMIC_RST_DEB_100MS 0x02
259+
#define T_PMIC_RST_DEB_500MS 0x03
260+
#define T_PMIC_RST_DEB_1S 0x04
261+
#define T_PMIC_RST_DEB_2S 0x05
262+
#define T_PMIC_RST_DEB_4S 0x06
263+
#define T_PMIC_RST_DEB_8S 0x07
232264

233265
/* PCA9450_REG_CONFIG2 bits */
234266
#define I2C_LT_MASK 0x03

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