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ASoC: convert from clk round_rate() to
Merge series from Brian Masney <bmasney@redhat.com>: The round_rate() clk ops is deprecated in the clk framework in favor of the determine_rate() clk ops, so let's go ahead and convert the drivers in the rtc subsystem using the Coccinelle semantic patch posted below. I did a few minor cosmetic cleanups of the code in a few cases. Coccinelle semantic patch: virtual patch // Look up the current name of the round_rate function @ has_round_rate @ identifier round_rate_name =~ ".*_round_rate"; identifier hw_param, rate_param, parent_rate_param; @@ long round_rate_name(struct clk_hw *hw_param, unsigned long rate_param, unsigned long *parent_rate_param) { ... } // Rename the route_rate function name to determine_rate() @ script:python generate_name depends on has_round_rate @ round_rate_name << has_round_rate.round_rate_name; new_name; @@ coccinelle.new_name = round_rate_name.replace("_round_rate", "_determine_rate") // Change rate to req->rate; also change occurrences of 'return XXX'. @ chg_rate depends on generate_name @ identifier has_round_rate.round_rate_name; identifier has_round_rate.hw_param; identifier has_round_rate.rate_param; identifier has_round_rate.parent_rate_param; identifier ERR =~ "E.*"; expression E; @@ long round_rate_name(struct clk_hw *hw_param, unsigned long rate_param, unsigned long *parent_rate_param) { <... ( -return -ERR; +return -ERR; | - return rate_param; + return 0; | - return E; + req->rate = E; + + return 0; | - rate_param + req->rate ) ...> } // Coccinelle only transforms the first occurrence of the rate parameter // Run a second time. FIXME: Is there a better way to do this? @ chg_rate2 depends on generate_name @ identifier has_round_rate.round_rate_name; identifier has_round_rate.hw_param; identifier has_round_rate.rate_param; identifier has_round_rate.parent_rate_param; @@ long round_rate_name(struct clk_hw *hw_param, unsigned long rate_param, unsigned long *parent_rate_param) { <... - rate_param + req->rate ...> } // Change parent_rate to req->best_parent_rate @ chg_parent_rate depends on generate_name @ identifier has_round_rate.round_rate_name; identifier has_round_rate.hw_param; identifier has_round_rate.rate_param; identifier has_round_rate.parent_rate_param; @@ long round_rate_name(struct clk_hw *hw_param, unsigned long rate_param, unsigned long *parent_rate_param) { <... ( - *parent_rate_param + req->best_parent_rate | - parent_rate_param + &req->best_parent_rate ) ...> } // Convert the function definition from round_rate() to determine_rate() @ func_definition depends on chg_rate @ identifier has_round_rate.round_rate_name; identifier has_round_rate.hw_param; identifier has_round_rate.rate_param; identifier has_round_rate.parent_rate_param; identifier generate_name.new_name; @@ - long round_rate_name(struct clk_hw *hw_param, unsigned long rate_param, - unsigned long *parent_rate_param) + int new_name(struct clk_hw *hw, struct clk_rate_request *req) { ... } // Update the ops from round_rate() to determine_rate() @ ops depends on func_definition @ identifier has_round_rate.round_rate_name; identifier generate_name.new_name; @@ { ..., - .round_rate = round_rate_name, + .determine_rate = new_name, ..., } Note that I used coccinelle 1.2 instead of 1.3 since the newer version adds unnecessary braces as described in this post. https://lore.kernel.org/cocci/67642477-5f3e-4b2a-914d-579a54f48cbd@intel.com/
2 parents bfd2912 + d5f317f commit dd10ed1

6 files changed

Lines changed: 87 additions & 72 deletions

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‎sound/soc/codecs/da7219.c‎

Lines changed: 34 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1982,8 +1982,8 @@ static unsigned long da7219_wclk_recalc_rate(struct clk_hw *hw,
19821982
}
19831983
}
19841984

1985-
static long da7219_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
1986-
unsigned long *parent_rate)
1985+
static int da7219_wclk_determine_rate(struct clk_hw *hw,
1986+
struct clk_rate_request *req)
19871987
{
19881988
struct da7219_priv *da7219 =
19891989
container_of(hw, struct da7219_priv,
@@ -1992,28 +1992,30 @@ static long da7219_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
19921992
if (!da7219->master)
19931993
return -EINVAL;
19941994

1995-
if (rate < 11025)
1996-
return 8000;
1997-
else if (rate < 12000)
1998-
return 11025;
1999-
else if (rate < 16000)
2000-
return 12000;
2001-
else if (rate < 22050)
2002-
return 16000;
2003-
else if (rate < 24000)
2004-
return 22050;
2005-
else if (rate < 32000)
2006-
return 24000;
2007-
else if (rate < 44100)
2008-
return 32000;
2009-
else if (rate < 48000)
2010-
return 44100;
2011-
else if (rate < 88200)
2012-
return 48000;
2013-
else if (rate < 96000)
2014-
return 88200;
1995+
if (req->rate < 11025)
1996+
req->rate = 8000;
1997+
else if (req->rate < 12000)
1998+
req->rate = 11025;
1999+
else if (req->rate < 16000)
2000+
req->rate = 12000;
2001+
else if (req->rate < 22050)
2002+
req->rate = 16000;
2003+
else if (req->rate < 24000)
2004+
req->rate = 22050;
2005+
else if (req->rate < 32000)
2006+
req->rate = 24000;
2007+
else if (req->rate < 44100)
2008+
req->rate = 32000;
2009+
else if (req->rate < 48000)
2010+
req->rate = 44100;
2011+
else if (req->rate < 88200)
2012+
req->rate = 48000;
2013+
else if (req->rate < 96000)
2014+
req->rate = 88200;
20152015
else
2016-
return 96000;
2016+
req->rate = 96000;
2017+
2018+
return 0;
20172019
}
20182020

20192021
static int da7219_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2070,15 +2072,15 @@ static unsigned long da7219_bclk_get_factor(unsigned long rate,
20702072
return 256;
20712073
}
20722074

2073-
static long da7219_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2074-
unsigned long *parent_rate)
2075+
static int da7219_bclk_determine_rate(struct clk_hw *hw,
2076+
struct clk_rate_request *req)
20752077
{
20762078
struct da7219_priv *da7219 =
20772079
container_of(hw, struct da7219_priv,
20782080
dai_clks_hw[DA7219_DAI_BCLK_IDX]);
20792081
unsigned long factor;
20802082

2081-
if (!*parent_rate || !da7219->master)
2083+
if (!req->best_parent_rate || !da7219->master)
20822084
return -EINVAL;
20832085

20842086
/*
@@ -2088,9 +2090,11 @@ static long da7219_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
20882090
* parent WCLK rate set and find the appropriate multiplier of BCLK to
20892091
* get the rounded down BCLK value.
20902092
*/
2091-
factor = da7219_bclk_get_factor(rate, *parent_rate);
2093+
factor = da7219_bclk_get_factor(req->rate, req->best_parent_rate);
2094+
2095+
req->rate = req->best_parent_rate * factor;
20922096

2093-
return *parent_rate * factor;
2097+
return 0;
20942098
}
20952099

20962100
static int da7219_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2116,12 +2120,12 @@ static const struct clk_ops da7219_dai_clk_ops[DA7219_DAI_NUM_CLKS] = {
21162120
.unprepare = da7219_wclk_unprepare,
21172121
.is_prepared = da7219_wclk_is_prepared,
21182122
.recalc_rate = da7219_wclk_recalc_rate,
2119-
.round_rate = da7219_wclk_round_rate,
2123+
.determine_rate = da7219_wclk_determine_rate,
21202124
.set_rate = da7219_wclk_set_rate,
21212125
},
21222126
[DA7219_DAI_BCLK_IDX] = {
21232127
.recalc_rate = da7219_bclk_recalc_rate,
2124-
.round_rate = da7219_bclk_round_rate,
2128+
.determine_rate = da7219_bclk_determine_rate,
21252129
.set_rate = da7219_bclk_set_rate,
21262130
},
21272131
};

‎sound/soc/codecs/rt5682.c‎

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2675,8 +2675,8 @@ static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
26752675
return rt5682->lrck[RT5682_AIF1];
26762676
}
26772677

2678-
static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2679-
unsigned long *parent_rate)
2678+
static int rt5682_wclk_determine_rate(struct clk_hw *hw,
2679+
struct clk_rate_request *req)
26802680
{
26812681
struct rt5682_priv *rt5682 =
26822682
container_of(hw, struct rt5682_priv,
@@ -2689,13 +2689,13 @@ static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
26892689
* Only accept to set wclk rate to 44.1k or 48kHz.
26902690
* It will force to 48kHz if not both.
26912691
*/
2692-
if (rate != CLK_48 && rate != CLK_44) {
2692+
if (req->rate != CLK_48 && req->rate != CLK_44) {
26932693
dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
26942694
__func__, clk_name, CLK_44, CLK_48);
2695-
rate = CLK_48;
2695+
req->rate = CLK_48;
26962696
}
26972697

2698-
return rate;
2698+
return 0;
26992699
}
27002700

27012701
static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2795,15 +2795,15 @@ static unsigned long rt5682_bclk_get_factor(unsigned long rate,
27952795
return 256;
27962796
}
27972797

2798-
static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2799-
unsigned long *parent_rate)
2798+
static int rt5682_bclk_determine_rate(struct clk_hw *hw,
2799+
struct clk_rate_request *req)
28002800
{
28012801
struct rt5682_priv *rt5682 =
28022802
container_of(hw, struct rt5682_priv,
28032803
dai_clks_hw[RT5682_DAI_BCLK_IDX]);
28042804
unsigned long factor;
28052805

2806-
if (!*parent_rate || !rt5682_clk_check(rt5682))
2806+
if (!req->best_parent_rate || !rt5682_clk_check(rt5682))
28072807
return -EINVAL;
28082808

28092809
/*
@@ -2813,9 +2813,11 @@ static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
28132813
* and find the appropriate multiplier of BCLK to
28142814
* get the rounded down BCLK value.
28152815
*/
2816-
factor = rt5682_bclk_get_factor(rate, *parent_rate);
2816+
factor = rt5682_bclk_get_factor(req->rate, req->best_parent_rate);
2817+
2818+
req->rate = req->best_parent_rate * factor;
28172819

2818-
return *parent_rate * factor;
2820+
return 0;
28192821
}
28202822

28212823
static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2849,12 +2851,12 @@ static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
28492851
.prepare = rt5682_wclk_prepare,
28502852
.unprepare = rt5682_wclk_unprepare,
28512853
.recalc_rate = rt5682_wclk_recalc_rate,
2852-
.round_rate = rt5682_wclk_round_rate,
2854+
.determine_rate = rt5682_wclk_determine_rate,
28532855
.set_rate = rt5682_wclk_set_rate,
28542856
},
28552857
[RT5682_DAI_BCLK_IDX] = {
28562858
.recalc_rate = rt5682_bclk_recalc_rate,
2857-
.round_rate = rt5682_bclk_round_rate,
2859+
.determine_rate = rt5682_bclk_determine_rate,
28582860
.set_rate = rt5682_bclk_set_rate,
28592861
},
28602862
};

‎sound/soc/codecs/rt5682s.c‎

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2610,8 +2610,8 @@ static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw,
26102610
return rt5682s->lrck[RT5682S_AIF1];
26112611
}
26122612

2613-
static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2614-
unsigned long *parent_rate)
2613+
static int rt5682s_wclk_determine_rate(struct clk_hw *hw,
2614+
struct clk_rate_request *req)
26152615
{
26162616
struct rt5682s_priv *rt5682s =
26172617
container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
@@ -2624,13 +2624,13 @@ static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
26242624
* Only accept to set wclk rate to 44.1k or 48kHz.
26252625
* It will force to 48kHz if not both.
26262626
*/
2627-
if (rate != CLK_48 && rate != CLK_44) {
2627+
if (req->rate != CLK_48 && req->rate != CLK_44) {
26282628
dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
26292629
__func__, clk_name, CLK_44, CLK_48);
2630-
rate = CLK_48;
2630+
req->rate = CLK_48;
26312631
}
26322632

2633-
return rate;
2633+
return 0;
26342634
}
26352635

26362636
static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2719,14 +2719,14 @@ static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
27192719
return 256;
27202720
}
27212721

2722-
static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2723-
unsigned long *parent_rate)
2722+
static int rt5682s_bclk_determine_rate(struct clk_hw *hw,
2723+
struct clk_rate_request *req)
27242724
{
27252725
struct rt5682s_priv *rt5682s =
27262726
container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
27272727
unsigned long factor;
27282728

2729-
if (!*parent_rate || !rt5682s_clk_check(rt5682s))
2729+
if (!req->best_parent_rate || !rt5682s_clk_check(rt5682s))
27302730
return -EINVAL;
27312731

27322732
/*
@@ -2736,9 +2736,11 @@ static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
27362736
* and find the appropriate multiplier of BCLK to
27372737
* get the rounded down BCLK value.
27382738
*/
2739-
factor = rt5682s_bclk_get_factor(rate, *parent_rate);
2739+
factor = rt5682s_bclk_get_factor(req->rate, req->best_parent_rate);
2740+
2741+
req->rate = req->best_parent_rate * factor;
27402742

2741-
return *parent_rate * factor;
2743+
return 0;
27422744
}
27432745

27442746
static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -2769,12 +2771,12 @@ static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = {
27692771
.prepare = rt5682s_wclk_prepare,
27702772
.unprepare = rt5682s_wclk_unprepare,
27712773
.recalc_rate = rt5682s_wclk_recalc_rate,
2772-
.round_rate = rt5682s_wclk_round_rate,
2774+
.determine_rate = rt5682s_wclk_determine_rate,
27732775
.set_rate = rt5682s_wclk_set_rate,
27742776
},
27752777
[RT5682S_DAI_BCLK_IDX] = {
27762778
.recalc_rate = rt5682s_bclk_recalc_rate,
2777-
.round_rate = rt5682s_bclk_round_rate,
2779+
.determine_rate = rt5682s_bclk_determine_rate,
27782780
.set_rate = rt5682s_bclk_set_rate,
27792781
},
27802782
};

‎sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -69,17 +69,17 @@ static unsigned long clk_q6dsp_recalc_rate(struct clk_hw *hw,
6969
return clk->rate;
7070
}
7171

72-
static long clk_q6dsp_round_rate(struct clk_hw *hw, unsigned long rate,
73-
unsigned long *parent_rate)
72+
static int clk_q6dsp_determine_rate(struct clk_hw *hw,
73+
struct clk_rate_request *req)
7474
{
75-
return rate;
75+
return 0;
7676
}
7777

7878
static const struct clk_ops clk_q6dsp_ops = {
7979
.prepare = clk_q6dsp_prepare,
8080
.unprepare = clk_q6dsp_unprepare,
8181
.set_rate = clk_q6dsp_set_rate,
82-
.round_rate = clk_q6dsp_round_rate,
82+
.determine_rate = clk_q6dsp_determine_rate,
8383
.recalc_rate = clk_q6dsp_recalc_rate,
8484
};
8585

‎sound/soc/stm/stm32_i2s.c‎

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -461,20 +461,25 @@ static int stm32_i2s_set_parent_rate(struct stm32_i2s_data *i2s,
461461
return -EINVAL;
462462
}
463463

464-
static long stm32_i2smclk_round_rate(struct clk_hw *hw, unsigned long rate,
465-
unsigned long *prate)
464+
static int stm32_i2smclk_determine_rate(struct clk_hw *hw,
465+
struct clk_rate_request *req)
466466
{
467467
struct stm32_i2smclk_data *mclk = to_mclk_data(hw);
468468
struct stm32_i2s_data *i2s = mclk->i2s_data;
469469
int ret;
470470

471-
ret = stm32_i2s_calc_clk_div(i2s, *prate, rate);
472-
if (ret)
473-
return ret;
471+
ret = stm32_i2s_calc_clk_div(i2s, req->best_parent_rate, req->rate);
472+
if (ret) {
473+
req->rate = ret;
474474

475-
mclk->freq = *prate / i2s->divider;
475+
return 0;
476+
}
476477

477-
return mclk->freq;
478+
mclk->freq = req->best_parent_rate / i2s->divider;
479+
480+
req->rate = mclk->freq;
481+
482+
return 0;
478483
}
479484

480485
static unsigned long stm32_i2smclk_recalc_rate(struct clk_hw *hw,
@@ -530,7 +535,7 @@ static const struct clk_ops mclk_ops = {
530535
.enable = stm32_i2smclk_enable,
531536
.disable = stm32_i2smclk_disable,
532537
.recalc_rate = stm32_i2smclk_recalc_rate,
533-
.round_rate = stm32_i2smclk_round_rate,
538+
.determine_rate = stm32_i2smclk_determine_rate,
534539
.set_rate = stm32_i2smclk_set_rate,
535540
};
536541

‎sound/soc/stm/stm32_sai_sub.c‎

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -489,20 +489,22 @@ static int stm32_sai_set_parent_rate(struct stm32_sai_sub_data *sai,
489489
return -EINVAL;
490490
}
491491

492-
static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
493-
unsigned long *prate)
492+
static int stm32_sai_mclk_determine_rate(struct clk_hw *hw,
493+
struct clk_rate_request *req)
494494
{
495495
struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
496496
struct stm32_sai_sub_data *sai = mclk->sai_data;
497497
int div;
498498

499-
div = stm32_sai_get_clk_div(sai, *prate, rate);
499+
div = stm32_sai_get_clk_div(sai, req->best_parent_rate, req->rate);
500500
if (div <= 0)
501501
return -EINVAL;
502502

503-
mclk->freq = *prate / div;
503+
mclk->freq = req->best_parent_rate / div;
504504

505-
return mclk->freq;
505+
req->rate = mclk->freq;
506+
507+
return 0;
506508
}
507509

508510
static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
@@ -558,7 +560,7 @@ static const struct clk_ops mclk_ops = {
558560
.enable = stm32_sai_mclk_enable,
559561
.disable = stm32_sai_mclk_disable,
560562
.recalc_rate = stm32_sai_mclk_recalc_rate,
561-
.round_rate = stm32_sai_mclk_round_rate,
563+
.determine_rate = stm32_sai_mclk_determine_rate,
562564
.set_rate = stm32_sai_mclk_set_rate,
563565
};
564566

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