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dt-bindings: clock: mediatek: Describe MT8196 clock controllers
Introduce binding documentation for system clocks, functional clocks, and PEXTP0/1 and UFS reset controllers on MediaTek MT8196. This binding also includes a handle to the hardware voter, a fixed-function MCU designed to aggregate votes from the application processor and other remote processors to manage clocks and power domains. The HWV on MT8196/MT6991 is incomplete and requires software to manually enable power supplies, parent clocks, and FENC, as well as write to both the HWV MMIO and the controller registers. Because of these constraints, the HWV cannot be modeled using generic clock, power domain, or interconnect APIs. Instead, a custom phandle is exceptionally used to provide direct, syscon-like register access to drivers. Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Functional Clock Controller for MT8196
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maintainers:
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- Guangjie Song <guangjie.song@mediatek.com>
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- Laura Nao <laura.nao@collabora.com>
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description: |
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The clock architecture in MediaTek SoCs is structured like below:
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The device nodes provide clock gate control in different IP blocks.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8196-imp-iic-wrap-c
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- mediatek,mt8196-imp-iic-wrap-e
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- mediatek,mt8196-imp-iic-wrap-n
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- mediatek,mt8196-imp-iic-wrap-w
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- mediatek,mt8196-mdpsys0
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- mediatek,mt8196-mdpsys1
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- mediatek,mt8196-pericfg-ao
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- mediatek,mt8196-pextp0cfg-ao
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- mediatek,mt8196-pextp1cfg-ao
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- mediatek,mt8196-ufscfg-ao
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- mediatek,mt8196-vencsys
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- mediatek,mt8196-vencsys-c1
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- mediatek,mt8196-vencsys-c2
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- mediatek,mt8196-vdecsys
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- mediatek,mt8196-vdecsys-soc
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- mediatek,mt8196-vdisp-ao
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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description:
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Reset lines for PEXTP0/1 and UFS blocks.
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mediatek,hardware-voter:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: |
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Phandle to the "Hardware Voter" (HWV), as named in the vendor
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documentation for MT8196/MT6991.
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The HWV is a SoC-internal fixed-function MCU used to collect votes from
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both the Application Processor and other remote processors within the SoC.
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It is intended to transparently enable or disable hardware resources (such
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as power domains or clocks) based on internal vote aggregation handled by
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the MCU's internal state machine.
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However, in practice, this design is incomplete. While the HWV performs
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some internal vote aggregation,software is still required to
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- Manually enable power supplies externally, if present and if required
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- Manually enable parent clocks via direct MMIO writes to clock controllers
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- Enable the FENC after the clock has been ungated via direct MMIO
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writes to clock controllers
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As such, the HWV behaves more like a hardware-managed clock reference
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counter than a true voter. Furthermore, it is not a separate
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controller. It merely serves as an alternative interface to the same
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underlying clock or power controller. Actual control still requires
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direct access to the controller's own MMIO register space, in
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addition to writing to the HWV's MMIO region.
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For this reason, a custom phandle is used here - drivers need to directly
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access the HWV MMIO region in a syscon-like fashion, due to how the
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hardware is wired. This differs from true hardware voting systems, which
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typically do not require custom phandles and rely instead on generic APIs
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(clocks, power domains, interconnects).
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The name "hardware-voter" is retained to match vendor documentation, but
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this should not be reused or misunderstood as a proper voting mechanism.
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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pericfg_ao: clock-controller@16640000 {
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compatible = "mediatek,mt8196-pericfg-ao", "syscon";
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reg = <0x16640000 0x1000>;
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mediatek,hardware-voter = <&scp_hwv>;
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#clock-cells = <1>;
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};
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- |
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pextp0cfg_ao: clock-controller@169b0000 {
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compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";
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reg = <0x169b0000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek System Clock Controller for MT8196
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maintainers:
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- Guangjie Song <guangjie.song@mediatek.com>
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- Laura Nao <laura.nao@collabora.com>
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description: |
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The clock architecture in MediaTek SoCs is structured like below:
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll
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provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
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The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which
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provide the clock source to other IP blocks.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8196-apmixedsys
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- mediatek,mt8196-armpll-b-pll-ctrl
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- mediatek,mt8196-armpll-bl-pll-ctrl
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- mediatek,mt8196-armpll-ll-pll-ctrl
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- mediatek,mt8196-apmixedsys-gp2
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- mediatek,mt8196-ccipll-pll-ctrl
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- mediatek,mt8196-mfgpll-pll-ctrl
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- mediatek,mt8196-mfgpll-sc0-pll-ctrl
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- mediatek,mt8196-mfgpll-sc1-pll-ctrl
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- mediatek,mt8196-ptppll-pll-ctrl
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- mediatek,mt8196-topckgen
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- mediatek,mt8196-topckgen-gp2
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- mediatek,mt8196-vlpckgen
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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mediatek,hardware-voter:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: |
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Phandle to the "Hardware Voter" (HWV), as named in the vendor
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documentation for MT8196/MT6991.
56+
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The HWV is a SoC-internal fixed-function MCU used to collect votes from
58+
both the Application Processor and other remote processors within the SoC.
59+
It is intended to transparently enable or disable hardware resources (such
60+
as power domains or clocks) based on internal vote aggregation handled by
61+
the MCU's internal state machine.
62+
63+
However, in practice, this design is incomplete. While the HWV performs
64+
some internal vote aggregation,software is still required to
65+
- Manually enable power supplies externally, if present and if required
66+
- Manually enable parent clocks via direct MMIO writes to clock controllers
67+
- Enable the FENC after the clock has been ungated via direct MMIO
68+
writes to clock controllers
69+
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As such, the HWV behaves more like a hardware-managed clock reference
71+
counter than a true voter. Furthermore, it is not a separate
72+
controller. It merely serves as an alternative interface to the same
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underlying clock or power controller. Actual control still requires
74+
direct access to the controller's own MMIO register space, in
75+
addition to writing to the HWV's MMIO region.
76+
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For this reason, a custom phandle is used here - drivers need to directly
78+
access the HWV MMIO region in a syscon-like fashion, due to how the
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hardware is wired. This differs from true hardware voting systems, which
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typically do not require custom phandles and rely instead on generic APIs
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(clocks, power domains, interconnects).
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The name "hardware-voter" is retained to match vendor documentation, but
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this should not be reused or misunderstood as a proper voting mechanism.
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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apmixedsys_clk: syscon@10000800 {
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compatible = "mediatek,mt8196-apmixedsys", "syscon";
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reg = <0x10000800 0x1000>;
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#clock-cells = <1>;
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};
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- |
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt8196-topckgen", "syscon";
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reg = <0x10000000 0x800>;
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mediatek,hardware-voter = <&scp_hwv>;
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#clock-cells = <1>;
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};
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