drm/asahi: Implement ASAHI_BIND_SINGLE_PAGE

Signed-off-by: Asahi Lina <lina@asahilina.net>

Author: hoshinolina

drivers/gpu/drm/asahi/file.rs

@@ -249,7 +249,8 @@ impl File {
 
             feat_compat: gpu.get_cfg().gpu_feat_compat
                 | hw::feat::compat::GETTIME
-                | hw::feat::compat::USER_TIMESTAMPS,
+                | hw::feat::compat::USER_TIMESTAMPS
+                | hw::feat::compat::SINGLE_PAGE_MAP,
             feat_incompat: gpu.get_cfg().gpu_feat_incompat,
 
             gpu_generation: gpu.get_dyncfg().id.gpu_gen as u32,
@@ -561,11 +562,16 @@ impl File {
             return Err(EINVAL); // Must be page aligned
         }
 
-        if (data.flags & !(uapi::ASAHI_BIND_READ | uapi::ASAHI_BIND_WRITE)) != 0 {
+        if (data.flags
+            & !(uapi::ASAHI_BIND_READ | uapi::ASAHI_BIND_WRITE | uapi::ASAHI_BIND_SINGLE_PAGE))
+            != 0
+        {
             cls_pr_debug!(Errors, "gem_bind: Invalid flags {:#x}\n", data.flags);
             return Err(EINVAL);
         }
 
+        let single_page = data.flags & uapi::ASAHI_BIND_SINGLE_PAGE != 0;
+
         let bo = gem::lookup_handle(file, data.handle)?;
 
         let start = data.addr;
@@ -625,7 +631,14 @@ impl File {
             return Err(EINVAL);
         }
 
-        vm.bind_object(&bo.gem, data.addr, data.range, data.offset, prot)?;
+        vm.bind_object(
+            &bo.gem,
+            data.addr,
+            data.range,
+            data.offset,
+            prot,
+            single_page,
+        )?;
 
         Ok(0)
     }

drivers/gpu/drm/asahi/hw/mod.rs

@@ -99,6 +99,9 @@ pub(crate) mod feat {
         /// User timestamps extension supported
         pub(crate) const USER_TIMESTAMPS: u64 =
             uapi::drm_asahi_feat_compat_DRM_ASAHI_FEAT_USER_TIMESTAMPS as u64;
+        /// User timestamps extension supported
+        pub(crate) const SINGLE_PAGE_MAP: u64 =
+            uapi::drm_asahi_feat_compat_DRM_ASAHI_FEAT_SINGLE_PAGE_MAP as u64;
     }
 
     /// Backwards-incompatible features.

drivers/gpu/drm/asahi/mmu.rs

@@ -192,6 +192,8 @@ impl gpuvm::DriverGpuVm for VmInner {
 
         let bo = ctx.vm_bo.as_ref().expect("step_map with no BO");
 
+        let one_page = op.flags().contains(gpuvm::GpuVaFlags::SINGLE_PAGE);
+
         let guard = bo.inner().sgt.lock();
         for range in guard.as_ref().expect("step_map with no SGT").iter() {
             let mut addr = range.dma_address();
@@ -214,18 +216,27 @@ impl gpuvm::DriverGpuVm for VmInner {
 
             assert!(offset == 0);
 
-            len = len.min(left);
+            if one_page {
+                len = left;
+            } else {
+                len = len.min(left);
+            }
 
             mod_dev_dbg!(
                 self.dev,
-                "MMU: map: {:#x}:{:#x} -> {:#x}\n",
+                "MMU: map: {:#x}:{:#x} -> {:#x} [OP={}]\n",
                 addr,
                 len,
-                iova
+                iova,
+                one_page
             );
 
-            self.page_table
-                .map_pages(iova..(iova + len as u64), addr as PhysicalAddr, ctx.prot)?;
+            self.page_table.map_pages(
+                iova..(iova + len as u64),
+                addr as PhysicalAddr,
+                ctx.prot,
+                one_page,
+            )?;
 
             left -= len;
             iova += len as u64;
@@ -437,8 +448,12 @@ impl VmInner {
                 iova
             );
 
-            self.page_table
-                .map_pages(iova..(iova + len as u64), addr as PhysicalAddr, prot)?;
+            self.page_table.map_pages(
+                iova..(iova + len as u64),
+                addr as PhysicalAddr,
+                prot,
+                false,
+            )?;
 
             iova += len as u64;
             left -= len;
@@ -1084,6 +1099,7 @@ impl Vm {
         size: u64,
         offset: u64,
         prot: Prot,
+        single_page: bool,
     ) -> Result {
         // Mapping needs a complete context
         let mut ctx = StepContext {
@@ -1118,14 +1134,20 @@ impl Vm {
             return Err(EINVAL);
         }
 
+        let flags = if single_page {
+            gpuvm::GpuVaFlags::SINGLE_PAGE
+        } else {
+            gpuvm::GpuVaFlags::NONE
+        };
+
         mod_dev_dbg!(
             inner.dev,
             "MMU: sm_map: {:#x} [{:#x}] -> {:#x}\n",
             offset,
             size,
             addr
         );
-        inner.sm_map(&mut ctx, addr, size, offset)
+        inner.sm_map(&mut ctx, addr, size, offset, flags)
     }
 
     /// Add a direct MMIO mapping to this Vm at a free address.
@@ -1173,10 +1195,12 @@ impl Vm {
             0,
         )?;
 
-        let ret =
-            inner
-                .page_table
-                .map_pages(iova..(iova + size as u64), phys as PhysicalAddr, prot);
+        let ret = inner.page_table.map_pages(
+            iova..(iova + size as u64),
+            phys as PhysicalAddr,
+            prot,
+            false,
+        );
         // Drop the exec_lock first, so that if map_node failed the
         // KernelMappingInner destructur does not deadlock.
         core::mem::drop(inner);

drivers/gpu/drm/asahi/pgtable.rs

@@ -385,6 +385,7 @@ impl UatPageTable {
         iova_range: Range<u64>,
         mut phys: PhysicalAddr,
         prot: Prot,
+        one_page: bool,
     ) -> Result {
         mod_pr_debug!(
             "UATPageTable::map_pages: {:#x?} {:#x?} {:?}\n",
@@ -411,7 +412,9 @@ impl UatPageTable {
                     phys | prot.as_pte() | PTE_TYPE_LEAF_TABLE,
                     Ordering::Relaxed,
                 );
-                phys += UAT_PGSZ as PhysicalAddr;
+                if !one_page {
+                    phys += UAT_PGSZ as PhysicalAddr;
+                }
             }
         })
     }