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drm/i915/wm: convert i9xx_wm.h external interfaces to struct intel_display
Going forward, struct intel_display is the main display device data pointer. Convert the i9xx_wm.h interface to struct intel_display. With this, we can make intel_wm.c independent of i915_drv.h. v2: Also remove i915_drv.h, fix commit message Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/3e30634d85c0e0aac9c95f9a2f928131ba400271.1744119460.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
1 parent 3b9c794 commit ddb062b

5 files changed

Lines changed: 37 additions & 32 deletions

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‎drivers/gpu/drm/i915/display/i9xx_wm.c‎

Lines changed: 19 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,7 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
200200

201201
/**
202202
* intel_set_memory_cxsr - Configure CxSR state
203-
* @dev_priv: i915 device
203+
* @display: display device
204204
* @enable: Allow vs. disallow CxSR
205205
*
206206
* Allow or disallow the system to enter a special CxSR
@@ -235,8 +235,9 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
235235
* the hardware w.r.t. HPLL SR when writing to plane registers.
236236
* Disallowing just CxSR is sufficient.
237237
*/
238-
bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
238+
bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
239239
{
240+
struct drm_i915_private *dev_priv = to_i915(display->drm);
240241
bool ret;
241242

242243
mutex_lock(&dev_priv->display.wm.wm_mutex);
@@ -652,7 +653,7 @@ static void pnv_update_wm(struct intel_display *display)
652653
latency = pnv_get_cxsr_latency(dev_priv);
653654
if (!latency) {
654655
drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
655-
intel_set_memory_cxsr(dev_priv, false);
656+
intel_set_memory_cxsr(display, false);
656657
return;
657658
}
658659

@@ -702,9 +703,9 @@ static void pnv_update_wm(struct intel_display *display)
702703
intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), reg);
703704
drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
704705

705-
intel_set_memory_cxsr(dev_priv, true);
706+
intel_set_memory_cxsr(display, true);
706707
} else {
707-
intel_set_memory_cxsr(dev_priv, false);
708+
intel_set_memory_cxsr(display, false);
708709
}
709710
}
710711

@@ -2177,7 +2178,7 @@ static void i965_update_wm(struct intel_display *display)
21772178
} else {
21782179
cxsr_enabled = false;
21792180
/* Turn off self refresh if both pipes are enabled */
2180-
intel_set_memory_cxsr(dev_priv, false);
2181+
intel_set_memory_cxsr(display, false);
21812182
}
21822183

21832184
drm_dbg_kms(&dev_priv->drm,
@@ -2198,7 +2199,7 @@ static void i965_update_wm(struct intel_display *display)
21982199
FW_WM(cursor_sr, CURSOR_SR));
21992200

22002201
if (cxsr_enabled)
2201-
intel_set_memory_cxsr(dev_priv, true);
2202+
intel_set_memory_cxsr(display, true);
22022203
}
22032204

22042205
#undef FW_WM
@@ -2307,7 +2308,7 @@ static void i9xx_update_wm(struct intel_display *display)
23072308
cwm = 2;
23082309

23092310
/* Play safe and disable self-refresh before adjusting watermarks. */
2310-
intel_set_memory_cxsr(dev_priv, false);
2311+
intel_set_memory_cxsr(display, false);
23112312

23122313
/* Calc sr entries for one plane configs */
23132314
if (HAS_FW_BLC(dev_priv) && crtc) {
@@ -2359,7 +2360,7 @@ static void i9xx_update_wm(struct intel_display *display)
23592360
intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
23602361

23612362
if (crtc)
2362-
intel_set_memory_cxsr(dev_priv, true);
2363+
intel_set_memory_cxsr(display, true);
23632364
}
23642365

23652366
static void i845_update_wm(struct intel_display *display)
@@ -3411,8 +3412,10 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
34113412
dev_priv->display.wm.hw = *results;
34123413
}
34133414

3414-
bool ilk_disable_cxsr(struct drm_i915_private *dev_priv)
3415+
bool ilk_disable_cxsr(struct intel_display *display)
34153416
{
3417+
struct drm_i915_private *dev_priv = to_i915(display->drm);
3418+
34163419
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
34173420
}
34183421

@@ -3580,8 +3583,9 @@ static int ilk_sanitize_watermarks_add_affected(struct drm_atomic_state *state)
35803583
* through the atomic check code to calculate new watermark values in the
35813584
* state object.
35823585
*/
3583-
void ilk_wm_sanitize(struct drm_i915_private *dev_priv)
3586+
void ilk_wm_sanitize(struct intel_display *display)
35843587
{
3588+
struct drm_i915_private *dev_priv = to_i915(display->drm);
35853589
struct drm_atomic_state *state;
35863590
struct intel_atomic_state *intel_state;
35873591
struct intel_crtc *crtc;
@@ -4156,8 +4160,10 @@ static const struct intel_wm_funcs i845_wm_funcs = {
41564160
static const struct intel_wm_funcs nop_funcs = {
41574161
};
41584162

4159-
void i9xx_wm_init(struct drm_i915_private *dev_priv)
4163+
void i9xx_wm_init(struct intel_display *display)
41604164
{
4165+
struct drm_i915_private *dev_priv = to_i915(display->drm);
4166+
41614167
/* For FIFO watermark updates */
41624168
if (HAS_PCH_SPLIT(dev_priv)) {
41634169
ilk_setup_wm_latency(dev_priv);
@@ -4172,7 +4178,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
41724178
if (!pnv_get_cxsr_latency(dev_priv)) {
41734179
drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n");
41744180
/* Disable CxSR and never update its watermark again */
4175-
intel_set_memory_cxsr(dev_priv, false);
4181+
intel_set_memory_cxsr(display, false);
41764182
dev_priv->display.funcs.wm = &nop_funcs;
41774183
} else {
41784184
dev_priv->display.funcs.wm = &pnv_wm_funcs;

‎drivers/gpu/drm/i915/display/i9xx_wm.h‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -8,28 +8,28 @@
88

99
#include <linux/types.h>
1010

11-
struct drm_i915_private;
1211
struct intel_crtc_state;
12+
struct intel_display;
1313
struct intel_plane_state;
1414

1515
#ifdef I915
16-
bool ilk_disable_cxsr(struct drm_i915_private *i915);
17-
void ilk_wm_sanitize(struct drm_i915_private *i915);
18-
bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable);
19-
void i9xx_wm_init(struct drm_i915_private *i915);
16+
bool ilk_disable_cxsr(struct intel_display *display);
17+
void ilk_wm_sanitize(struct intel_display *display);
18+
bool intel_set_memory_cxsr(struct intel_display *display, bool enable);
19+
void i9xx_wm_init(struct intel_display *display);
2020
#else
21-
static inline bool ilk_disable_cxsr(struct drm_i915_private *i915)
21+
static inline bool ilk_disable_cxsr(struct intel_display *display)
2222
{
2323
return false;
2424
}
25-
static inline void ilk_wm_sanitize(struct drm_i915_private *i915)
25+
static inline void ilk_wm_sanitize(struct intel_display *display)
2626
{
2727
}
28-
static inline bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable)
28+
static inline bool intel_set_memory_cxsr(struct intel_display *display, bool enable)
2929
{
3030
return false;
3131
}
32-
static inline void i9xx_wm_init(struct drm_i915_private *i915)
32+
static inline void i9xx_wm_init(struct intel_display *display)
3333
{
3434
}
3535
#endif

‎drivers/gpu/drm/i915/display/intel_display.c‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -664,7 +664,6 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
664664
struct intel_plane *plane)
665665
{
666666
struct intel_display *display = to_intel_display(crtc);
667-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
668667
struct intel_crtc_state *crtc_state =
669668
to_intel_crtc_state(crtc->base.state);
670669
struct intel_plane_state *plane_state =
@@ -697,7 +696,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
697696
* wait-for-vblank between disabling the plane and the pipe.
698697
*/
699698
if (HAS_GMCH(display) &&
700-
intel_set_memory_cxsr(dev_priv, false))
699+
intel_set_memory_cxsr(display, false))
701700
intel_plane_initial_vblank_wait(crtc);
702701

703702
/*
@@ -1169,7 +1168,6 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
11691168
struct intel_crtc *crtc)
11701169
{
11711170
struct intel_display *display = to_intel_display(state);
1172-
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
11731171
const struct intel_crtc_state *old_crtc_state =
11741172
intel_atomic_get_old_crtc_state(state, crtc);
11751173
const struct intel_crtc_state *new_crtc_state =
@@ -1223,7 +1221,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
12231221
* wait-for-vblank between disabling the plane and the pipe.
12241222
*/
12251223
if (HAS_GMCH(display) && old_crtc_state->hw.active &&
1226-
new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1224+
new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false))
12271225
intel_crtc_wait_for_next_vblank(crtc);
12281226

12291227
/*
@@ -1234,7 +1232,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
12341232
* WaCxSRDisabledForSpriteScaling:ivb
12351233
*/
12361234
if (!HAS_GMCH(display) && old_crtc_state->hw.active &&
1237-
new_crtc_state->disable_cxsr && ilk_disable_cxsr(dev_priv))
1235+
new_crtc_state->disable_cxsr && ilk_disable_cxsr(display))
12381236
intel_crtc_wait_for_next_vblank(crtc);
12391237

12401238
/*

‎drivers/gpu/drm/i915/display/intel_display_driver.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -476,7 +476,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
476476
* since the watermark calculation done here will use pstate->fb.
477477
*/
478478
if (!HAS_GMCH(display))
479-
ilk_wm_sanitize(i915);
479+
ilk_wm_sanitize(display);
480480

481481
return 0;
482482

‎drivers/gpu/drm/i915/display/intel_wm.c‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,11 @@
55

66
#include <linux/debugfs.h>
77

8-
#include "i915_drv.h"
8+
#include <drm/drm_file.h>
9+
#include <drm/drm_print.h>
10+
911
#include "i9xx_wm.h"
12+
#include "intel_display_core.h"
1013
#include "intel_display_types.h"
1114
#include "intel_wm.h"
1215
#include "skl_watermark.h"
@@ -169,12 +172,10 @@ void intel_print_wm_latency(struct intel_display *display,
169172

170173
void intel_wm_init(struct intel_display *display)
171174
{
172-
struct drm_i915_private *i915 = to_i915(display->drm);
173-
174175
if (DISPLAY_VER(display) >= 9)
175176
skl_wm_init(display);
176177
else
177-
i9xx_wm_init(i915);
178+
i9xx_wm_init(display);
178179
}
179180

180181
static void wm_latency_show(struct seq_file *m, const u16 wm[8])

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