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Merge branch 'pci/controller/s32g'
- Add NXP S32G host controller DT binding and driver (Vincent Guittot) * pci/controller/s32g: MAINTAINERS: Add NXP S32G PCIe controller driver maintainer PCI: s32g: Add NXP S32G PCIe controller driver (RC) PCI: dwc: Add register and bitfield definitions dt-bindings: PCI: s32g: Add NXP S32G PCIe controller
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‎Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/nxp,s32g-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP S32G2xxx/S32G3xxx PCIe Root Complex controller
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maintainers:
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- Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
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- Ionut Vicovan <ionut.vicovan@nxp.com>
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description:
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This PCIe controller is based on the Synopsys DesignWare PCIe IP.
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The S32G SoC family has two PCIe controllers, which can be configured as
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either Root Complex or Endpoint.
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properties:
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compatible:
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oneOf:
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- enum:
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- nxp,s32g2-pcie
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- items:
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- const: nxp,s32g3-pcie
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- const: nxp,s32g2-pcie
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reg:
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maxItems: 6
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: atu
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- const: dma
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- const: ctrl
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- const: config
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interrupts:
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minItems: 1
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maxItems: 2
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interrupt-names:
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items:
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- const: msi
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- const: dma
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minItems: 1
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pcie@0:
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description:
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Describe the S32G Root Port.
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type: object
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$ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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reg:
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maxItems: 1
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phys:
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maxItems: 1
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required:
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- reg
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- phys
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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- ranges
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- pcie@0
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@40400000 {
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compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie";
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reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */
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<0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */
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<0x00 0x40460000 0x0 0x00001000>, /* atu registers */
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<0x00 0x40470000 0x0 0x00001000>, /* dma registers */
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<0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */
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<0x5f 0xffffe000 0x0 0x00002000>; /* config space */
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reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config";
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dma-coherent;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges =
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<0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,
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<0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>,
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<0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>;
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bus-range = <0x0 0xff>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi", "dma";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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pcie@0 {
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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device_type = "pci";
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phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
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};
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};
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};

‎MAINTAINERS‎

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@@ -3132,6 +3132,15 @@ F: arch/arm64/boot/dts/freescale/s32g*.dts*
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F: drivers/pinctrl/nxp/
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F: drivers/rtc/rtc-s32g.c
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ARM/NXP S32G PCIE CONTROLLER DRIVER
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M: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
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R: NXP S32 Linux Team <s32@nxp.com>
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L: imx@lists.linux.dev
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
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F: drivers/pci/controller/dwc/pcie-nxp-s32g*
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ARM/NXP S32G/S32R DWMAC ETHERNET DRIVER
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M: Jan Petrous <jan.petrous@oss.nxp.com>
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R: s32@nxp.com

‎drivers/pci/controller/dwc/Kconfig‎

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in order to enable device-specific features PCIE_TEGRA194_EP must be
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selected. This uses the DesignWare core.
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config PCIE_NXP_S32G
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bool "NXP S32G PCIe controller (host mode)"
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depends on ARCH_S32 || COMPILE_TEST
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select PCIE_DW_HOST
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help
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Enable support for the PCIe controller in NXP S32G based boards to
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work in Host mode. The controller is based on DesignWare IP and
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can work either as RC or EP. In order to enable host-specific
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features PCIE_NXP_S32G must be selected.
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config PCIE_DW_PLAT
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bool
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‎drivers/pci/controller/dwc/Makefile‎

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@@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
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obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
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obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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obj-$(CONFIG_PCIE_NXP_S32G) += pcie-nxp-s32g.o
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obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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# ARM32 platforms use hook_fault_code() and cannot support loadable module.
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obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o

‎drivers/pci/controller/dwc/pcie-designware.h‎

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#define GEN3_RELATED_OFF 0x890
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#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
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#define GEN3_RELATED_OFF_EQ_PHASE_2_3 BIT(9)
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#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
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#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
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#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
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#define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA GENMASK(13, 10)
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#define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA GENMASK(17, 14)
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#define COHERENCY_CONTROL_1_OFF 0x8E0
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#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK GENMASK(31, 2)
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#define CFG_MEMTYPE_VALUE BIT(0)
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#define COHERENCY_CONTROL_2_OFF 0x8E4
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#define COHERENCY_CONTROL_3_OFF 0x8E8
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#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
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#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
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