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clk: mediatek: Add MT8196 ovl0 clock support
Add support for the MT8196 ovl0 clock controller, which provides clock gate control for the display system. It is integrated with the mtk-mmsys driver, which registers the ovl0 clock driver via platform_device_register_data(). Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Lines changed: 156 additions & 1 deletion

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‎drivers/clk/mediatek/Makefile‎

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@@ -157,7 +157,8 @@ obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o clk-mt8196-vdisp_ao.o \
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clk-mt8196-ovl0.o
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obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
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obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o

‎drivers/clk/mediatek/clk-mt8196-ovl0.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs ovl0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs ovl0_hwv_regs = {
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.set_ofs = 0x0060,
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.clr_ofs = 0x0064,
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.sta_ofs = 0x2c30,
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};
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static const struct mtk_gate_regs ovl1_cg_regs = {
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.set_ofs = 0x114,
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.clr_ofs = 0x118,
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.sta_ofs = 0x110,
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};
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static const struct mtk_gate_regs ovl1_hwv_regs = {
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.set_ofs = 0x0068,
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.clr_ofs = 0x006c,
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.sta_ofs = 0x2c34,
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};
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#define GATE_HWV_OVL0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ovl0_cg_regs, \
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.hwv_regs = &ovl0_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_OVL1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ovl1_cg_regs, \
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.hwv_regs = &ovl1_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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static const struct mtk_gate ovl_clks[] = {
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/* OVL0 */
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GATE_HWV_OVL0(CLK_OVLSYS_CONFIG, "ovlsys_config", "disp", 0),
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GATE_HWV_OVL0(CLK_OVL_FAKE_ENG0, "ovl_fake_eng0", "disp", 1),
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GATE_HWV_OVL0(CLK_OVL_FAKE_ENG1, "ovl_fake_eng1", "disp", 2),
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GATE_HWV_OVL0(CLK_OVL_MUTEX0, "ovl_mutex0", "disp", 3),
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GATE_HWV_OVL0(CLK_OVL_EXDMA0, "ovl_exdma0", "disp", 4),
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GATE_HWV_OVL0(CLK_OVL_EXDMA1, "ovl_exdma1", "disp", 5),
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GATE_HWV_OVL0(CLK_OVL_EXDMA2, "ovl_exdma2", "disp", 6),
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GATE_HWV_OVL0(CLK_OVL_EXDMA3, "ovl_exdma3", "disp", 7),
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GATE_HWV_OVL0(CLK_OVL_EXDMA4, "ovl_exdma4", "disp", 8),
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GATE_HWV_OVL0(CLK_OVL_EXDMA5, "ovl_exdma5", "disp", 9),
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GATE_HWV_OVL0(CLK_OVL_EXDMA6, "ovl_exdma6", "disp", 10),
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GATE_HWV_OVL0(CLK_OVL_EXDMA7, "ovl_exdma7", "disp", 11),
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GATE_HWV_OVL0(CLK_OVL_EXDMA8, "ovl_exdma8", "disp", 12),
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GATE_HWV_OVL0(CLK_OVL_EXDMA9, "ovl_exdma9", "disp", 13),
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GATE_HWV_OVL0(CLK_OVL_BLENDER0, "ovl_blender0", "disp", 14),
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GATE_HWV_OVL0(CLK_OVL_BLENDER1, "ovl_blender1", "disp", 15),
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GATE_HWV_OVL0(CLK_OVL_BLENDER2, "ovl_blender2", "disp", 16),
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GATE_HWV_OVL0(CLK_OVL_BLENDER3, "ovl_blender3", "disp", 17),
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GATE_HWV_OVL0(CLK_OVL_BLENDER4, "ovl_blender4", "disp", 18),
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GATE_HWV_OVL0(CLK_OVL_BLENDER5, "ovl_blender5", "disp", 19),
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GATE_HWV_OVL0(CLK_OVL_BLENDER6, "ovl_blender6", "disp", 20),
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GATE_HWV_OVL0(CLK_OVL_BLENDER7, "ovl_blender7", "disp", 21),
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GATE_HWV_OVL0(CLK_OVL_BLENDER8, "ovl_blender8", "disp", 22),
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GATE_HWV_OVL0(CLK_OVL_BLENDER9, "ovl_blender9", "disp", 23),
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GATE_HWV_OVL0(CLK_OVL_OUTPROC0, "ovl_outproc0", "disp", 24),
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GATE_HWV_OVL0(CLK_OVL_OUTPROC1, "ovl_outproc1", "disp", 25),
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GATE_HWV_OVL0(CLK_OVL_OUTPROC2, "ovl_outproc2", "disp", 26),
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GATE_HWV_OVL0(CLK_OVL_OUTPROC3, "ovl_outproc3", "disp", 27),
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GATE_HWV_OVL0(CLK_OVL_OUTPROC4, "ovl_outproc4", "disp", 28),
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GATE_HWV_OVL0(CLK_OVL_OUTPROC5, "ovl_outproc5", "disp", 29),
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GATE_HWV_OVL0(CLK_OVL_MDP_RSZ0, "ovl_mdp_rsz0", "disp", 30),
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GATE_HWV_OVL0(CLK_OVL_MDP_RSZ1, "ovl_mdp_rsz1", "disp", 31),
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/* OVL1 */
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GATE_HWV_OVL1(CLK_OVL_DISP_WDMA0, "ovl_disp_wdma0", "disp", 0),
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GATE_HWV_OVL1(CLK_OVL_DISP_WDMA1, "ovl_disp_wdma1", "disp", 1),
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GATE_HWV_OVL1(CLK_OVL_UFBC_WDMA0, "ovl_ufbc_wdma0", "disp", 2),
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GATE_HWV_OVL1(CLK_OVL_MDP_RDMA0, "ovl_mdp_rdma0", "disp", 3),
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GATE_HWV_OVL1(CLK_OVL_MDP_RDMA1, "ovl_mdp_rdma1", "disp", 4),
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GATE_HWV_OVL1(CLK_OVL_BWM0, "ovl_bwm0", "disp", 5),
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GATE_HWV_OVL1(CLK_OVL_DLI0, "ovl_dli0", "disp", 6),
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GATE_HWV_OVL1(CLK_OVL_DLI1, "ovl_dli1", "disp", 7),
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GATE_HWV_OVL1(CLK_OVL_DLI2, "ovl_dli2", "disp", 8),
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GATE_HWV_OVL1(CLK_OVL_DLI3, "ovl_dli3", "disp", 9),
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GATE_HWV_OVL1(CLK_OVL_DLI4, "ovl_dli4", "disp", 10),
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GATE_HWV_OVL1(CLK_OVL_DLI5, "ovl_dli5", "disp", 11),
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GATE_HWV_OVL1(CLK_OVL_DLI6, "ovl_dli6", "disp", 12),
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GATE_HWV_OVL1(CLK_OVL_DLI7, "ovl_dli7", "disp", 13),
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GATE_HWV_OVL1(CLK_OVL_DLI8, "ovl_dli8", "disp", 14),
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GATE_HWV_OVL1(CLK_OVL_DLO0, "ovl_dlo0", "disp", 15),
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GATE_HWV_OVL1(CLK_OVL_DLO1, "ovl_dlo1", "disp", 16),
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GATE_HWV_OVL1(CLK_OVL_DLO2, "ovl_dlo2", "disp", 17),
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GATE_HWV_OVL1(CLK_OVL_DLO3, "ovl_dlo3", "disp", 18),
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GATE_HWV_OVL1(CLK_OVL_DLO4, "ovl_dlo4", "disp", 19),
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GATE_HWV_OVL1(CLK_OVL_DLO5, "ovl_dlo5", "disp", 20),
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GATE_HWV_OVL1(CLK_OVL_DLO6, "ovl_dlo6", "disp", 21),
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GATE_HWV_OVL1(CLK_OVL_DLO7, "ovl_dlo7", "disp", 22),
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GATE_HWV_OVL1(CLK_OVL_DLO8, "ovl_dlo8", "disp", 23),
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GATE_HWV_OVL1(CLK_OVL_DLO9, "ovl_dlo9", "disp", 24),
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GATE_HWV_OVL1(CLK_OVL_DLO10, "ovl_dlo10", "disp", 25),
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GATE_HWV_OVL1(CLK_OVL_DLO11, "ovl_dlo11", "disp", 26),
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GATE_HWV_OVL1(CLK_OVL_DLO12, "ovl_dlo12", "disp", 27),
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GATE_HWV_OVL1(CLK_OVLSYS_RELAY0, "ovlsys_relay0", "disp", 28),
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GATE_HWV_OVL1(CLK_OVL_INLINEROT0, "ovl_inlinerot0", "disp", 29),
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GATE_HWV_OVL1(CLK_OVL_SMI, "ovl_smi", "disp", 30),
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};
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static const struct mtk_clk_desc ovl_mcd = {
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.clks = ovl_clks,
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.num_clks = ARRAY_SIZE(ovl_clks),
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};
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static const struct platform_device_id clk_mt8196_ovl0_id_table[] = {
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{ .name = "clk-mt8196-ovl0", .driver_data = (kernel_ulong_t)&ovl_mcd },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(platform, clk_mt8196_ovl0_id_table);
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static struct platform_driver clk_mt8196_ovl0_drv = {
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.probe = mtk_clk_pdev_probe,
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.remove = mtk_clk_pdev_remove,
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.driver = {
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.name = "clk-mt8196-ovl0",
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},
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.id_table = clk_mt8196_ovl0_id_table,
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};
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module_platform_driver(clk_mt8196_ovl0_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 ovl0 clocks driver");
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MODULE_LICENSE("GPL");

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