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marcanjannau
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wifi: brcmfmac: Handle watchdog properly in newer cores
On newer cores, we need to explicitly set the subsystems to reset via the watchdog. Logic adapted from bcmdhd. Signed-off-by: Hector Martin <marcan@marcan.st>
1 parent 03d5c3d commit e766c78

2 files changed

Lines changed: 32 additions & 2 deletions

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drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -736,8 +736,30 @@ static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
736736

737737
/* Watchdog reset */
738738
brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
739-
WRITECC32(devinfo, watchdog, 4);
740-
msleep(100);
739+
core = brcmf_chip_get_chipcommon(devinfo->ci);
740+
741+
if (core->rev >= 65) {
742+
u32 mask = CC_WD_SSRESET_PCIE_F0_EN;
743+
744+
core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
745+
if (core->rev < 66)
746+
mask |= CC_WD_SSRESET_PCIE_ALL_FN_EN;
747+
748+
val = READCC32(devinfo, watchdog);
749+
val &= ~CC_WD_ENABLE_MASK;
750+
val |= mask;
751+
WRITECC32(devinfo, watchdog, val);
752+
val &= ~CC_WD_COUNTER_MASK;
753+
val |= 4;
754+
WRITECC32(devinfo, watchdog, val);
755+
msleep(10);
756+
val = READCC32(devinfo, intstatus);
757+
val |= mask;
758+
WRITECC32(devinfo, intstatus, val);
759+
} else {
760+
WRITECC32(devinfo, watchdog, 4);
761+
msleep(100);
762+
}
741763

742764
/* Restore ASPM */
743765
brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);

drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -302,6 +302,14 @@ struct chipcregs {
302302
#define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27)
303303

304304

305+
/* watchdog */
306+
#define CC_WD_SSRESET_PCIE_F0_EN 0x10000000
307+
#define CC_WD_SSRESET_PCIE_F1_EN 0x20000000
308+
#define CC_WD_SSRESET_PCIE_F2_EN 0x40000000
309+
#define CC_WD_SSRESET_PCIE_ALL_FN_EN 0x80000000
310+
#define CC_WD_COUNTER_MASK 0x0fffffff
311+
#define CC_WD_ENABLE_MASK 0xf0000000
312+
305313
/*
306314
* Maximum delay for the PMU state transition in us.
307315
* This is an upper bound intended for spinwaits etc.

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