@@ -92,6 +92,7 @@ struct lpspi_config {
9292 u8 prescale ;
9393 u16 mode ;
9494 u32 speed_hz ;
95+ u32 effective_speed_hz ;
9596};
9697
9798struct fsl_lpspi_data {
@@ -315,9 +316,10 @@ static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
315316static int fsl_lpspi_set_bitrate (struct fsl_lpspi_data * fsl_lpspi )
316317{
317318 struct lpspi_config config = fsl_lpspi -> config ;
318- unsigned int perclk_rate , scldiv , div ;
319+ unsigned int perclk_rate , div ;
319320 u8 prescale_max ;
320321 u8 prescale ;
322+ int scldiv ;
321323
322324 perclk_rate = clk_get_rate (fsl_lpspi -> clk_per );
323325 prescale_max = fsl_lpspi -> devtype_data -> prescale_max ;
@@ -338,19 +340,22 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
338340
339341 for (prescale = 0 ; prescale <= prescale_max ; prescale ++ ) {
340342 scldiv = div / (1 << prescale ) - 2 ;
341- if (scldiv < 256 ) {
343+ if (scldiv >= 0 && scldiv < 256 ) {
342344 fsl_lpspi -> config .prescale = prescale ;
343345 break ;
344346 }
345347 }
346348
347- if (scldiv >= 256 )
349+ if (scldiv < 0 || scldiv >= 256 )
348350 return - EINVAL ;
349351
350352 writel (scldiv | (scldiv << 8 ) | ((scldiv >> 1 ) << 16 ),
351353 fsl_lpspi -> base + IMX7ULP_CCR );
352354
353- dev_dbg (fsl_lpspi -> dev , "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n" ,
355+ fsl_lpspi -> config .effective_speed_hz = perclk_rate / (scldiv + 2 ) *
356+ (1 << prescale );
357+
358+ dev_dbg (fsl_lpspi -> dev , "perclk=%u, speed=%u, prescale=%u, scldiv=%d\n" ,
354359 perclk_rate , config .speed_hz , prescale , scldiv );
355360
356361 return 0 ;
@@ -749,6 +754,8 @@ static int fsl_lpspi_transfer_one(struct spi_controller *controller,
749754 if (ret < 0 )
750755 return ret ;
751756
757+ t -> effective_speed_hz = fsl_lpspi -> config .effective_speed_hz ;
758+
752759 fsl_lpspi_set_cmd (fsl_lpspi );
753760 fsl_lpspi -> is_first_byte = false;
754761
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