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Qiang Yuvinodkoul
Qiang Yu
authored and
vinodkoul
committed
phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3
Currently driver supports only x4 lane based functionality using tx/rx and tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3, PCIe3 related QMP PHY provides additional programming which are available as txz and rxz based register set. Hence add txz and rxz based registers usage and programming sequences. As soon as software programs the txz and rxz based register set, hardware shall "broadcast" the same settings to the tx/rx pair of registers for all the 8 lanes, which saves the effort of software programming them one by one. There might be some tx and/or rx registers on some lanes need minor tweaks, program them after programming the txz and rxz reigster set. In addition, x1e80100 uses QMP PHY ver 6.30 for PCIe Gen4 x8, hence add two new header files to reflect the new register offsets. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20241017030412.265000-5-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
1 parent 26fb23c commit e961ec8

3 files changed

Lines changed: 258 additions & 0 deletions

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‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c‎

Lines changed: 214 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,8 @@
3434
#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
3535
#include "phy-qcom-qmp-pcs-pcie-v6.h"
3636
#include "phy-qcom-qmp-pcs-pcie-v6_20.h"
37+
#include "phy-qcom-qmp-pcs-pcie-v6_30.h"
38+
#include "phy-qcom-qmp-pcs-v6_30.h"
3739
#include "phy-qcom-qmp-pcie-qhp.h"
3840

3941
#define PHY_INIT_COMPLETE_TIMEOUT 10000
@@ -1344,6 +1346,154 @@ static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
13441346
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a),
13451347
};
13461348

1349+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_serdes_tbl[] = {
1350+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
1351+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1352+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1353+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1354+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1355+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x08),
1356+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x04),
1357+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0d),
1358+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
1359+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
1360+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
1361+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
1362+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
1363+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1364+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1365+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1366+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1367+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1368+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1369+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1370+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1371+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1372+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1373+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1374+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1375+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1376+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1377+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1378+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1379+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1380+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1381+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c),
1382+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1383+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1384+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1385+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1386+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1387+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1388+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1389+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1390+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
1391+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1392+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1393+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1394+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1395+
};
1396+
1397+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl[] = {
1398+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1399+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
1400+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
1401+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
1402+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
1403+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
1404+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1405+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1406+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1407+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
1408+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1409+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1410+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1411+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1412+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1413+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1414+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1415+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1416+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1417+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1418+
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1419+
};
1420+
1421+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_txz_tbl[] = {
1422+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1423+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x05),
1424+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1425+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10),
1426+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1427+
QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1428+
};
1429+
1430+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rxz_tbl[] = {
1431+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
1432+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
1433+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1434+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1435+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1436+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1437+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00),
1438+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15),
1439+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),
1440+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0c),
1441+
QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
1442+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1443+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1444+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1445+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1446+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1447+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
1448+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd4),
1449+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0x23),
1450+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1451+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1452+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x38),
1453+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1454+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1455+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x1c),
1456+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xe4),
1457+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),
1458+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1459+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x69),
1460+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1461+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1462+
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
1463+
};
1464+
1465+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rx_tbl[] = {
1466+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, BIT(0)),
1467+
};
1468+
1469+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_tbl[] = {
1470+
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2, 0x00),
1471+
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_G3S2_PRE_GAIN, 0x2e),
1472+
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_RX_SIGDET_LVL, 0x99),
1473+
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7, 0x00),
1474+
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG4, 0x00),
1475+
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG5, 0x22),
1476+
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG, 0x04),
1477+
QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG2, 0x02),
1478+
};
1479+
1480+
static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl[] = {
1481+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1482+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS, 0x00),
1483+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_EQ_CONFIG1, 0x16),
1484+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5, 0x02),
1485+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN, 0x2e),
1486+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1, 0x03),
1487+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3, 0x28),
1488+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5, 0x18),
1489+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5, 0x7a),
1490+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5, 0x8a),
1491+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME, 0x27),
1492+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME, 0x27),
1493+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG, 0xc0),
1494+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2, 0x1d),
1495+
};
1496+
13471497
static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
13481498
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
13491499
QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
@@ -2582,6 +2732,8 @@ struct qmp_pcie_offsets {
25822732
u16 rx;
25832733
u16 tx2;
25842734
u16 rx2;
2735+
u16 txz;
2736+
u16 rxz;
25852737
u16 ln_shrd;
25862738
};
25872739

@@ -2592,6 +2744,10 @@ struct qmp_phy_cfg_tbls {
25922744
int tx_num;
25932745
const struct qmp_phy_init_tbl *rx;
25942746
int rx_num;
2747+
const struct qmp_phy_init_tbl *txz;
2748+
int txz_num;
2749+
const struct qmp_phy_init_tbl *rxz;
2750+
int rxz_num;
25952751
const struct qmp_phy_init_tbl *pcs;
25962752
int pcs_num;
25972753
const struct qmp_phy_init_tbl *pcs_misc;
@@ -2659,6 +2815,8 @@ struct qmp_pcie {
26592815
void __iomem *rx;
26602816
void __iomem *tx2;
26612817
void __iomem *rx2;
2818+
void __iomem *txz;
2819+
void __iomem *rxz;
26622820
void __iomem *ln_shrd;
26632821

26642822
void __iomem *port_b;
@@ -2826,6 +2984,17 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
28262984
.ln_shrd = 0x0e00,
28272985
};
28282986

2987+
static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = {
2988+
.serdes = 0x8800,
2989+
.pcs = 0x9000,
2990+
.pcs_misc = 0x9800,
2991+
.tx = 0x0000,
2992+
.rx = 0x0200,
2993+
.txz = 0xe000,
2994+
.rxz = 0xe200,
2995+
.ln_shrd = 0x8000,
2996+
};
2997+
28292998
static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
28302999
.lanes = 1,
28313000

@@ -3704,6 +3873,38 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {
37043873
.has_nocsr_reset = true,
37053874
};
37063875

3876+
static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
3877+
.lanes = 8,
3878+
3879+
.offsets = &qmp_pcie_offsets_v6_30,
3880+
.tbls = {
3881+
.serdes = x1e80100_qmp_gen4x8_pcie_serdes_tbl,
3882+
.serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_serdes_tbl),
3883+
.rx = x1e80100_qmp_gen4x8_pcie_rx_tbl,
3884+
.rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rx_tbl),
3885+
.txz = x1e80100_qmp_gen4x8_pcie_txz_tbl,
3886+
.txz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_txz_tbl),
3887+
.rxz = x1e80100_qmp_gen4x8_pcie_rxz_tbl,
3888+
.rxz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rxz_tbl),
3889+
.pcs = x1e80100_qmp_gen4x8_pcie_pcs_tbl,
3890+
.pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_tbl),
3891+
.pcs_misc = x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl,
3892+
.pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl),
3893+
.ln_shrd = x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl,
3894+
.ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl),
3895+
},
3896+
3897+
.reset_list = sdm845_pciephy_reset_l,
3898+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3899+
.vreg_list = sm8550_qmp_phy_vreg_l,
3900+
.num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
3901+
.regs = pciephy_v6_regs_layout,
3902+
3903+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3904+
.phy_status = PHYSTATUS_4_20,
3905+
.has_nocsr_reset = true,
3906+
};
3907+
37073908
static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
37083909
{
37093910
const struct qmp_phy_cfg *cfg = qmp->cfg;
@@ -3751,6 +3952,13 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c
37513952

37523953
qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);
37533954

3955+
/*
3956+
* Tx/Rx registers that require different settings than
3957+
* txz/rxz must be programmed after txz/rxz.
3958+
*/
3959+
qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num);
3960+
qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num);
3961+
37543962
qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1);
37553963
qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1);
37563964

@@ -4293,6 +4501,9 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
42934501
return PTR_ERR(qmp->port_b);
42944502
}
42954503

4504+
qmp->txz = base + offs->txz;
4505+
qmp->rxz = base + offs->rxz;
4506+
42964507
if (cfg->tbls.ln_shrd)
42974508
qmp->ln_shrd = base + offs->ln_shrd;
42984509

@@ -4478,6 +4689,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
44784689
}, {
44794690
.compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",
44804691
.data = &x1e80100_qmp_gen4x4_pciephy_cfg,
4692+
}, {
4693+
.compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy",
4694+
.data = &x1e80100_qmp_gen4x8_pciephy_cfg,
44814695
},
44824696
{ },
44834697
};

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved.
4+
*/
5+
6+
#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_30_H_
7+
#define QCOM_PHY_QMP_PCS_PCIE_V6_30_H_
8+
9+
/* Only for QMP V6_30 PHY - PCIE have different offsets than V6 */
10+
#define QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2 0x014
11+
#define QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG 0x020
12+
#define QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE 0x024
13+
#define QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS 0x098
14+
#define QPHY_PCIE_V6_30_PCS_EQ_CONFIG1 0x0a8
15+
#define QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME 0x0f8
16+
#define QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME 0x0fc
17+
#define QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5 0x110
18+
#define QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN 0x164
19+
#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1 0x184
20+
#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3 0x18c
21+
#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5 0x194
22+
#define QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5 0x1b4
23+
#define QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5 0x1c8
24+
25+
#endif

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved.
4+
*/
5+
6+
#ifndef QCOM_PHY_QMP_PCS_V6_30_H_
7+
#define QCOM_PHY_QMP_PCS_V6_30_H_
8+
9+
/* Only for QMP V6_30 PHY - PCIe PCS registers */
10+
#define QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2 0x0cc
11+
#define QPHY_V6_30_PCS_G3S2_PRE_GAIN 0x17c
12+
#define QPHY_V6_30_PCS_RX_SIGDET_LVL 0x194
13+
#define QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7 0x1dc
14+
#define QPHY_V6_30_PCS_TX_RX_CONFIG 0x1e0
15+
#define QPHY_V6_30_PCS_TX_RX_CONFIG2 0x1e4
16+
#define QPHY_V6_30_PCS_EQ_CONFIG4 0x1fc
17+
#define QPHY_V6_30_PCS_EQ_CONFIG5 0x200
18+
19+
#endif

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