@@ -72,6 +72,27 @@ properties:
7272 power-domains :
7373 maxItems : 1
7474
75+ patternProperties :
76+ " ^pci@ " :
77+ $ref : /schemas/pci/pci-bus.yaml#
78+ type : object
79+ description : A single PCI root port
80+
81+ properties :
82+ reg :
83+ maxItems : 1
84+
85+ pwren-gpios :
86+ description : Optional GPIO to power on the device
87+ maxItems : 1
88+
89+ required :
90+ - reset-gpios
91+ - interrupt-controller
92+ - " #interrupt-cells"
93+ - interrupt-map-mask
94+ - interrupt-map
95+
7596required :
7697 - compatible
7798 - reg
@@ -142,34 +163,58 @@ examples:
142163 pinctrl-0 = <&pcie_pins>;
143164 pinctrl-names = "default";
144165
145- pci@0,0 {
166+ port00: pci@0,0 {
146167 device_type = "pci";
147168 reg = <0x0 0x0 0x0 0x0 0x0>;
148169 reset-gpios = <&pinctrl_ap 152 0>;
149170
150171 #address-cells = <3>;
151172 #size-cells = <2>;
152173 ranges;
174+
175+ interrupt-controller;
176+ #interrupt-cells = <1>;
177+ interrupt-map-mask = <0 0 0 7>;
178+ interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
179+ <0 0 0 2 &port00 0 0 0 1>,
180+ <0 0 0 3 &port00 0 0 0 2>,
181+ <0 0 0 4 &port00 0 0 0 3>;
153182 };
154183
155- pci@1,0 {
184+ port01: pci@1,0 {
156185 device_type = "pci";
157186 reg = <0x800 0x0 0x0 0x0 0x0>;
158187 reset-gpios = <&pinctrl_ap 153 0>;
159188
160189 #address-cells = <3>;
161190 #size-cells = <2>;
162191 ranges;
192+
193+ interrupt-controller;
194+ #interrupt-cells = <1>;
195+ interrupt-map-mask = <0 0 0 7>;
196+ interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
197+ <0 0 0 2 &port01 0 0 0 1>,
198+ <0 0 0 3 &port01 0 0 0 2>,
199+ <0 0 0 4 &port01 0 0 0 3>;
163200 };
164201
165- pci@2,0 {
202+ port02: pci@2,0 {
166203 device_type = "pci";
167204 reg = <0x1000 0x0 0x0 0x0 0x0>;
168205 reset-gpios = <&pinctrl_ap 33 0>;
169206
170207 #address-cells = <3>;
171208 #size-cells = <2>;
172209 ranges;
210+
211+ interrupt-controller;
212+ #interrupt-cells = <1>;
213+ interrupt-map-mask = <0 0 0 7>;
214+ interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
215+ <0 0 0 2 &port02 0 0 0 1>,
216+ <0 0 0 3 &port02 0 0 0 2>,
217+ <0 0 0 4 &port02 0 0 0 3>;
173218 };
174219 };
175220 };
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