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Kaustabh Chakrabortykrzk
Kaustabh Chakraborty
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krzk
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pinctrl: samsung: add support for exynos7870 pinctrl
Add support for the Exynos7870 SoC pin-controller in the pinctrl driver. It has 8 GPIO banks, and 3-bit PINCFG_TYPE_DRV width. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://lore.kernel.org/r/20250301-exynos7870-pinctrl-v3-3-ba1da9d3cd2f@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c‎

Lines changed: 139 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,15 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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/*
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* Bank type for alive type. Bit fields:
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* CON: 4, DAT: 1, PUD: 2, DRV: 3
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*/
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static const struct samsung_pin_bank_type exynos7870_bank_type_alive = {
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.fld_width = { 4, 1, 2, 3, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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/*
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* Bank type for non-alive type. Bit fields:
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* CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4
@@ -618,6 +627,136 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
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.num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl),
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};
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/* pin banks of exynos7870 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynos7870_pin_banks0[] __initconst = {
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EXYNOS7870_PIN_BANK_EINTN(6, 0x000, "etc0"),
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EXYNOS7870_PIN_BANK_EINTN(3, 0x020, "etc1"),
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EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00),
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EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04),
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EXYNOS7870_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08),
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EXYNOS7870_PIN_BANK_EINTN(2, 0x0c0, "gpq0"),
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};
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/* pin banks of exynos7870 pin-controller 1 (DISPAUD) */
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static const struct samsung_pin_bank_data exynos7870_pin_banks1[] __initconst = {
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EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpz0", 0x00),
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EXYNOS8895_PIN_BANK_EINTG(6, 0x020, "gpz1", 0x04),
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EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpz2", 0x08),
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};
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/* pin banks of exynos7870 pin-controller 2 (ESE) */
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static const struct samsung_pin_bank_data exynos7870_pin_banks2[] __initconst = {
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EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpc7", 0x00),
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};
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/* pin banks of exynos7870 pin-controller 3 (FSYS) */
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static const struct samsung_pin_bank_data exynos7870_pin_banks3[] __initconst = {
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EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpr0", 0x00),
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EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
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EXYNOS8895_PIN_BANK_EINTG(2, 0x040, "gpr2", 0x08),
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EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpr3", 0x0c),
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EXYNOS8895_PIN_BANK_EINTG(6, 0x080, "gpr4", 0x10),
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};
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/* pin banks of exynos7870 pin-controller 4 (MIF) */
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static const struct samsung_pin_bank_data exynos7870_pin_banks4[] __initconst = {
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EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "gpm0", 0x00),
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};
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/* pin banks of exynos7870 pin-controller 5 (NFC) */
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static const struct samsung_pin_bank_data exynos7870_pin_banks5[] __initconst = {
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EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpc2", 0x00),
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};
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/* pin banks of exynos7870 pin-controller 6 (TOP) */
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static const struct samsung_pin_bank_data exynos7870_pin_banks6[] __initconst = {
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EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpb0", 0x00),
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EXYNOS8895_PIN_BANK_EINTG(3, 0x020, "gpc0", 0x04),
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EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpc1", 0x08),
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EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpc4", 0x0c),
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EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpc5", 0x10),
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EXYNOS8895_PIN_BANK_EINTG(4, 0x0a0, "gpc6", 0x14),
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EXYNOS8895_PIN_BANK_EINTG(2, 0x0c0, "gpc8", 0x18),
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EXYNOS8895_PIN_BANK_EINTG(2, 0x0e0, "gpc9", 0x1c),
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EXYNOS8895_PIN_BANK_EINTG(7, 0x100, "gpd1", 0x20),
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EXYNOS8895_PIN_BANK_EINTG(6, 0x120, "gpd2", 0x24),
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EXYNOS8895_PIN_BANK_EINTG(8, 0x140, "gpd3", 0x28),
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EXYNOS8895_PIN_BANK_EINTG(7, 0x160, "gpd4", 0x2c),
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EXYNOS8895_PIN_BANK_EINTG(3, 0x1a0, "gpe0", 0x34),
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EXYNOS8895_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
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EXYNOS8895_PIN_BANK_EINTG(2, 0x1e0, "gpf1", 0x3c),
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EXYNOS8895_PIN_BANK_EINTG(2, 0x200, "gpf2", 0x40),
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EXYNOS8895_PIN_BANK_EINTG(4, 0x220, "gpf3", 0x44),
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EXYNOS8895_PIN_BANK_EINTG(5, 0x240, "gpf4", 0x48),
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};
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/* pin banks of exynos7870 pin-controller 7 (TOUCH) */
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static const struct samsung_pin_bank_data exynos7870_pin_banks7[] __initconst = {
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EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpc3", 0x00),
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};
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static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = {
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{
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/* pin-controller instance 0 Alive data */
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.pin_banks = exynos7870_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos7870_pin_banks0),
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.eint_wkup_init = exynos_eint_wkup_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 1 DISPAUD data */
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.pin_banks = exynos7870_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos7870_pin_banks1),
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}, {
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/* pin-controller instance 2 ESE data */
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.pin_banks = exynos7870_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos7870_pin_banks2),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 3 FSYS data */
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.pin_banks = exynos7870_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos7870_pin_banks3),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 4 MIF data */
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.pin_banks = exynos7870_pin_banks4,
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.nr_banks = ARRAY_SIZE(exynos7870_pin_banks4),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 5 NFC data */
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.pin_banks = exynos7870_pin_banks5,
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.nr_banks = ARRAY_SIZE(exynos7870_pin_banks5),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 6 TOP data */
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.pin_banks = exynos7870_pin_banks6,
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.nr_banks = ARRAY_SIZE(exynos7870_pin_banks6),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 7 TOUCH data */
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.pin_banks = exynos7870_pin_banks7,
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.nr_banks = ARRAY_SIZE(exynos7870_pin_banks7),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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},
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};
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const struct samsung_pinctrl_of_match_data exynos7870_of_data __initconst = {
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.ctrl = exynos7870_pin_ctrl,
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.num_ctrl = ARRAY_SIZE(exynos7870_pin_ctrl),
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};
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/* pin banks of exynos7885 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = {
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EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"),

‎drivers/pinctrl/samsung/pinctrl-exynos.h‎

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Original file line numberDiff line numberDiff line change
@@ -112,6 +112,25 @@
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.pctl_res_idx = pctl_idx, \
113113
} \
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#define EXYNOS7870_PIN_BANK_EINTN(pins, reg, id) \
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{ \
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.type = &exynos7870_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define EXYNOS7870_PIN_BANK_EINTW(pins, reg, id, offs) \
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{ \
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.type = &exynos7870_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \
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{ \
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.type = &exynos850_bank_type_alive, \

‎drivers/pinctrl/samsung/pinctrl-samsung.c‎

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Original file line numberDiff line numberDiff line change
@@ -1475,6 +1475,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
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.data = &exynos5433_of_data },
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{ .compatible = "samsung,exynos7-pinctrl",
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.data = &exynos7_of_data },
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{ .compatible = "samsung,exynos7870-pinctrl",
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.data = &exynos7870_of_data },
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{ .compatible = "samsung,exynos7885-pinctrl",
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.data = &exynos7885_of_data },
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{ .compatible = "samsung,exynos850-pinctrl",

‎drivers/pinctrl/samsung/pinctrl-samsung.h‎

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Original file line numberDiff line numberDiff line change
@@ -383,6 +383,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;

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