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Merge tag 'reset-for-v6.17' of https://git.pengutronix.de/git/pza/linux into soc/drivers
Reset controller updates for v6.17 * Support reset controllers on Kendryte K230 and SOPHGO CV1800B. * Add RZ/V2N USB2PHY reset controller bindings * Use auxiliary device creation helpers in reset-mpfs. * Convert nxp,lcp1850-rgu and snps,dw-reset binding docs to DT schema. * Enable reset-brcmstb(-rescal) on BCM2712. * Fix a typo in the T-HEAD TH1520 Kconfig option * tag 'reset-for-v6.17' of https://git.pengutronix.de/git/pza/linux: dt-bindings: reset: Convert snps,dw-reset to DT schema reset: brcmstb: Enable reset drivers for ARCH_BCM2835 reset: simple: add support for Sophgo CV1800B dt-bindings: reset: sophgo: Add CV1800B support reset: mpfs: use the auxiliary device creation dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/V2N SoC support dt-bindings: reset: convert nxp,lpc1850-rgu.txt to yaml format reset: thead: Fix TH1520 typo reset: canaan: add reset driver for Kendryte K230 dt-bindings: reset: add support for canaan,k230-rst Link: https://lore.kernel.org/r/20250710152513.1346298-1-p.zabel@pengutronix.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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‎Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/canaan,k230-rst.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Canaan Kendryte K230 Reset Controller
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maintainers:
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- Junhui Liu <junhui.liu@pigmoral.tech>
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description:
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The Canaan Kendryte K230 reset controller is part of the SoC's system
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controller and controls the reset registers for CPUs and various peripherals.
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properties:
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compatible:
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const: canaan,k230-rst
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reg:
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maxItems: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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reset-controller@91101000 {
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compatible = "canaan,k230-rst";
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reg = <0x91101000 0x1000>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt‎

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‎Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/nxp,lpc1850-rgu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP LPC1850 Reset Generation Unit (RGU)
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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properties:
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compatible:
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const: nxp,lpc1850-rgu
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reg:
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maxItems: 1
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: delay
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- const: reg
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'#reset-cells':
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const: 1
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description: |
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See table below for valid peripheral reset numbers. Numbers not
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in the table below are either reserved or not applicable for
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normal operation.
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Reset Peripheral
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9 System control unit (SCU)
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12 ARM Cortex-M0 subsystem core (LPC43xx only)
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13 CPU core
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16 LCD controller
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17 USB0
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18 USB1
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19 DMA
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20 SDIO
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21 External memory controller (EMC)
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22 Ethernet
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25 Flash bank A
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27 EEPROM
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28 GPIO
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29 Flash bank B
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32 Timer0
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33 Timer1
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34 Timer2
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35 Timer3
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36 Repetitive Interrupt timer (RIT)
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37 State Configurable Timer (SCT)
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38 Motor control PWM (MCPWM)
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39 QEI
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40 ADC0
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41 ADC1
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42 DAC
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44 USART0
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45 UART1
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46 USART2
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47 USART3
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48 I2C0
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49 I2C1
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50 SSP0
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51 SSP1
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52 I2S0 and I2S1
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53 Serial Flash Interface (SPIFI)
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54 C_CAN1
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55 C_CAN0
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56 ARM Cortex-M0 application core (LPC4370 only)
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57 SGPIO (LPC43xx only)
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58 SPI (LPC43xx only)
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60 ADCHS (12-bit ADC) (LPC4370 only)
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Refer to NXP LPC18xx or LPC43xx user manual for more details about
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the reset signals and the connected block/peripheral.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/lpc18xx-ccu.h>
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#include <dt-bindings/clock/lpc18xx-cgu.h>
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reset-controller@40053000 {
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compatible = "nxp,lpc1850-rgu";
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reg = <0x40053000 0x1000>;
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clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
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clock-names = "delay", "reg";
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#reset-cells = <1>;
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};
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‎Documentation/devicetree/bindings/reset/renesas,rzv2h-usb2phy-reset.yaml‎

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properties:
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compatible:
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const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P)
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oneOf:
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- items:
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- const: renesas,r9a09g056-usb2phy-reset # RZ/V2N
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- const: renesas,r9a09g057-usb2phy-reset
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- const: renesas,r9a09g057-usb2phy-reset # RZ/V2H(P)
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reg:
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maxItems: 1

‎Documentation/devicetree/bindings/reset/snps,dw-reset.txt‎

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‎Documentation/devicetree/bindings/reset/snps,dw-reset.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/snps,dw-reset.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare Reset controller
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maintainers:
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- Philipp Zabel <p.zabel@pengutronix.de>
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properties:
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compatible:
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enum:
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- snps,dw-high-reset
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- snps,dw-low-reset
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reg:
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maxItems: 1
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'#reset-cells':
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const: 1
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reset-controller: true
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required:
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- compatible
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- reg
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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reset-controller@0 {
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compatible = "snps,dw-high-reset";
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reg = <0x0000 0x4>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/reset/sophgo,sg2042-reset.yaml‎

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- enum:
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- sophgo,sg2044-reset
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- const: sophgo,sg2042-reset
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- const: sophgo,sg2042-reset
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- enum:
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- sophgo,cv1800b-reset
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- sophgo,sg2042-reset
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reg:
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maxItems: 1

‎drivers/reset/Kconfig‎

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config RESET_BRCMSTB
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tristate "Broadcom STB reset controller"
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depends on ARCH_BRCMSTB || COMPILE_TEST
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default ARCH_BRCMSTB
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depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
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default ARCH_BRCMSTB || ARCH_BCM2835
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help
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This enables the reset controller driver for Broadcom STB SoCs using
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a SUN_TOP_CTRL_SW_INIT style controller.
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config RESET_BRCMSTB_RESCAL
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tristate "Broadcom STB RESCAL reset controller"
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depends on HAS_IOMEM
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depends on ARCH_BRCMSTB || COMPILE_TEST
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default ARCH_BRCMSTB
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depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
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default ARCH_BRCMSTB || ARCH_BCM2835
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help
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This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
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BCM7216.
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BCM7216 or the BCM2712.
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config RESET_EYEQ
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bool "Mobileye EyeQ reset controller"
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Say Y if you want to control reset signals provided by this
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controller.
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config RESET_K230
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tristate "Reset controller driver for Canaan Kendryte K230 SoC"
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depends on ARCH_CANAAN || COMPILE_TEST
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depends on OF
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help
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Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
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Say Y if you want to control reset signals provided by this
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controller.
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config RESET_LANTIQ
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bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
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default SOC_TYPE_XWAY
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This enables the reset driver for Allwinner SoCs.
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config RESET_TH1520
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tristate "T-HEAD 1520 reset controller"
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tristate "T-HEAD TH1520 reset controller"
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depends on ARCH_THEAD || COMPILE_TEST
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select REGMAP_MMIO
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help

‎drivers/reset/Makefile‎

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obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o
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obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
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obj-$(CONFIG_RESET_K210) += reset-k210.o
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obj-$(CONFIG_RESET_K230) += reset-k230.o
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obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
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obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
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obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o

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