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dt-bindings: clock: qcom: document the Glymur Global Clock Controller
Add device tree bindings for global clock controller on Glymur SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-6-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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‎Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on Glymur SoC
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maintainers:
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- Taniya Das <taniya.das@oss.qualcomm.com>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on Glymur SoC.
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See also: include/dt-bindings/clock/qcom,glymur-gcc.h
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properties:
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compatible:
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const: qcom,glymur-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Board XO_A source
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- description: Sleep clock source
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- description: USB 0 Phy DP0 GMUX clock source
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- description: USB 0 Phy DP1 GMUX clock source
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- description: USB 0 Phy PCIE PIPEGMUX clock source
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- description: USB 0 Phy PIPEGMUX clock source
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- description: USB 0 Phy SYS PCIE PIPEGMUX clock source
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- description: USB 1 Phy DP0 GMUX 2 clock source
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- description: USB 1 Phy DP1 GMUX 2 clock source
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- description: USB 1 Phy PCIE PIPEGMUX clock source
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- description: USB 1 Phy PIPEGMUX clock source
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- description: USB 1 Phy SYS PCIE PIPEGMUX clock source
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- description: USB 2 Phy DP0 GMUX 2 clock source
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- description: USB 2 Phy DP1 GMUX 2 clock source
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- description: USB 2 Phy PCIE PIPEGMUX clock source
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- description: USB 2 Phy PIPEGMUX clock source
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- description: USB 2 Phy SYS PCIE PIPEGMUX clock source
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- description: PCIe 3a pipe clock
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- description: PCIe 3b pipe clock
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- description: PCIe 4 pipe clock
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- description: PCIe 5 pipe clock
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- description: PCIe 6 pipe clock
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- description: QUSB4 0 PHY RX 0 clock source
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- description: QUSB4 0 PHY RX 1 clock source
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- description: QUSB4 1 PHY RX 0 clock source
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- description: QUSB4 1 PHY RX 1 clock source
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- description: QUSB4 2 PHY RX 0 clock source
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- description: QUSB4 2 PHY RX 1 clock source
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- description: UFS PHY RX Symbol 0 clock source
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- description: UFS PHY RX Symbol 1 clock source
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- description: UFS PHY TX Symbol 0 clock source
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- description: USB3 PHY 0 pipe clock source
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- description: USB3 PHY 1 pipe clock source
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- description: USB3 PHY 2 pipe clock source
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- description: USB3 UNI PHY pipe 0 clock source
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- description: USB3 UNI PHY pipe 1 clock source
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- description: USB4 PHY 0 pcie pipe clock source
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- description: USB4 PHY 0 Max pipe clock source
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- description: USB4 PHY 1 pcie pipe clock source
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- description: USB4 PHY 1 Max pipe clock source
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- description: USB4 PHY 2 pcie pipe clock source
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- description: USB4 PHY 2 Max pipe clock source
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,glymur-gcc";
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reg = <0x100000 0x1f9000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>,
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<&usb_0_phy_dp0_gmux>,
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<&usb_0_phy_dp1_gmux>,
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<&usb_0_phy_pcie_pipegmux>,
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<&usb_0_phy_pipegmux>,
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<&usb_0_phy_sys_pcie_pipegmux>,
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<&usb_1_phy_dp0_gmux_2>,
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<&usb_1_phy_dp1_gmux_2>,
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<&usb_1_phy_pcie_pipegmux>,
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<&usb_1_phy_pipegmux>,
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<&usb_1_phy_sys_pcie_pipegmux>,
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<&usb_2_phy_dp0_gmux 2>,
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<&usb_2_phy_dp1_gmux 2>,
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<&usb_2_phy_pcie_pipegmux>,
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<&usb_2_phy_pipegmux>,
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<&usb_2_phy_sys_pcie_pipegmux>,
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<&pcie_3a_pipe>, <&pcie_3b_pipe>,
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<&pcie_4_pipe>, <&pcie_5_pipe>,
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<&pcie_6_pipe>,
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<&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>,
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<&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>,
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<&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>,
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<&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>,
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<&ufs_phy_tx_symbol_0>,
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<&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>,
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<&usb3_phy_2_pipe>,
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<&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>,
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<&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
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<&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
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<&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

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