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phy: renesas: Add Renesas RZ/G3E USB3.0 PHY driver
Add Renesas RZ/G3E USB3.0 PHY driver. This module is connected between USB3 Host and PHY module. The main functions of this module are: 1) Reset control 2) Control of PHY input pins 3) Monitoring of PHY output pins Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20251029084037.108610-3-biju.das.jz@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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‎drivers/phy/renesas/Kconfig‎

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@@ -40,3 +40,10 @@ config PHY_RCAR_GEN3_USB3
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select GENERIC_PHY
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help
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Support for USB 3.0 PHY found on Renesas R-Car generation 3 SoCs.
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config PHY_RZ_G3E_USB3
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tristate "Renesas RZ/G3E USB 3.0 PHY driver"
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depends on ARCH_RENESAS || COMPILE_TEST
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select GENERIC_PHY
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help
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Support for USB 3.0 PHY found on Renesas RZ/G3E SoCs.

‎drivers/phy/renesas/Makefile‎

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@@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
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obj-$(CONFIG_PHY_RCAR_GEN3_PCIE) += phy-rcar-gen3-pcie.o
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obj-$(CONFIG_PHY_RCAR_GEN3_USB2) += phy-rcar-gen3-usb2.o
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obj-$(CONFIG_PHY_RCAR_GEN3_USB3) += phy-rcar-gen3-usb3.o
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obj-$(CONFIG_PHY_RZ_G3E_USB3) += phy-rzg3e-usb3.o

‎drivers/phy/renesas/phy-rzg3e-usb3.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G3E USB3.0 PHY driver
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*
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* Copyright (C) 2025 Renesas Electronics Corporation
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#define USB3_TEST_RESET 0x0000
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#define USB3_TEST_UTMICTRL2 0x0b04
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#define USB3_TEST_PRMCTRL5_R 0x0c10
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#define USB3_TEST_PRMCTRL6_R 0x0c14
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#define USB3_TEST_RSTCTRL 0x1000
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#define USB3_TEST_CLKCTRL 0x1004
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#define USB3_TEST_RAMCTRL 0x100c
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#define USB3_TEST_CREGCTRL 0x1010
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#define USB3_TEST_LANECONFIG0 0x1030
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#define USB3_TEST_RESET_PORTRESET0_CTRL BIT(9)
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#define USB3_TEST_RESET_SIDDQ BIT(3)
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#define USB3_TEST_RESET_PHY_RESET BIT(2)
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#define USB3_TEST_RESET_PORTRESET0 BIT(1)
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#define USB3_TEST_RESET_RELEASE_OVERRIDE (0)
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#define USB3_TEST_UTMICTRL2_CTRL_MASK GENMASK(9, 8)
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#define USB3_TEST_UTMICTRL2_MODE_MASK GENMASK(1, 0)
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#define USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK GENMASK(2, 1)
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#define USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK GENMASK(2, 0)
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#define USB3_TEST_RSTCTRL_HARDRESET_ODEN BIT(9)
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#define USB3_TEST_RSTCTRL_PIPERESET_ODEN BIT(8)
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#define USB3_TEST_RSTCTRL_HARDRESET BIT(1)
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#define USB3_TEST_RSTCTRL_PIPERESET BIT(0)
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#define USB3_TEST_RSTCTRL_ASSERT \
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(USB3_TEST_RSTCTRL_HARDRESET_ODEN | USB3_TEST_RSTCTRL_PIPERESET_ODEN | \
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USB3_TEST_RSTCTRL_HARDRESET | USB3_TEST_RSTCTRL_PIPERESET)
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#define USB3_TEST_RSTCTRL_RELEASE_HARDRESET \
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(USB3_TEST_RSTCTRL_HARDRESET_ODEN | USB3_TEST_RSTCTRL_PIPERESET_ODEN | \
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USB3_TEST_RSTCTRL_PIPERESET)
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#define USB3_TEST_RSTCTRL_DEASSERT \
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(USB3_TEST_RSTCTRL_HARDRESET_ODEN | USB3_TEST_RSTCTRL_PIPERESET_ODEN)
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#define USB3_TEST_RSTCTRL_RELEASE_OVERRIDE (0)
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#define USB3_TEST_CLKCTRL_MPLLA_SSC_EN BIT(2)
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#define USB3_TEST_RAMCTRL_SRAM_INIT_DONE BIT(2)
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#define USB3_TEST_RAMCTRL_SRAM_EXT_LD_DONE BIT(0)
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#define USB3_TEST_CREGCTRL_PARA_SEL BIT(8)
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#define USB3_TEST_LANECONFIG0_DEFAULT (0xd)
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struct rz_usb3 {
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void __iomem *base;
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struct reset_control *rstc;
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bool skip_reinit;
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};
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static void rzg3e_phy_usb2test_phy_init(void __iomem *base)
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{
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u32 val;
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val = readl(base + USB3_TEST_UTMICTRL2);
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val |= USB3_TEST_UTMICTRL2_CTRL_MASK | USB3_TEST_UTMICTRL2_MODE_MASK;
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writel(val, base + USB3_TEST_UTMICTRL2);
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val = readl(base + USB3_TEST_PRMCTRL5_R);
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val &= ~USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK;
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val |= FIELD_PREP(USB3_TEST_PRMCTRL5_R_TXPREEMPAMPTUNE0_MASK, 2);
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writel(val, base + USB3_TEST_PRMCTRL5_R);
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val = readl(base + USB3_TEST_PRMCTRL6_R);
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val &= ~USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK;
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val |= FIELD_PREP(USB3_TEST_PRMCTRL6_R_OTGTUNE0_MASK, 7);
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writel(val, base + USB3_TEST_PRMCTRL6_R);
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val = readl(base + USB3_TEST_RESET);
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val &= ~USB3_TEST_RESET_SIDDQ;
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val |= USB3_TEST_RESET_PORTRESET0_CTRL | USB3_TEST_RESET_PHY_RESET |
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USB3_TEST_RESET_PORTRESET0;
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writel(val, base + USB3_TEST_RESET);
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fsleep(10);
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val &= ~(USB3_TEST_RESET_PHY_RESET | USB3_TEST_RESET_PORTRESET0);
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writel(val, base + USB3_TEST_RESET);
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fsleep(10);
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val = readl(base + USB3_TEST_UTMICTRL2);
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val &= ~USB3_TEST_UTMICTRL2_CTRL_MASK;
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writel(val, base + USB3_TEST_UTMICTRL2);
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writel(USB3_TEST_RESET_RELEASE_OVERRIDE, base + USB3_TEST_RESET);
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}
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static int rzg3e_phy_usb3test_phy_init(void __iomem *base)
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{
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int ret;
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u32 val;
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writel(USB3_TEST_CREGCTRL_PARA_SEL, base + USB3_TEST_CREGCTRL);
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writel(USB3_TEST_RSTCTRL_ASSERT, base + USB3_TEST_RSTCTRL);
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fsleep(20);
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writel(USB3_TEST_CLKCTRL_MPLLA_SSC_EN, base + USB3_TEST_CLKCTRL);
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writel(USB3_TEST_LANECONFIG0_DEFAULT, base + USB3_TEST_LANECONFIG0);
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writel(USB3_TEST_RSTCTRL_RELEASE_HARDRESET, base + USB3_TEST_RSTCTRL);
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ret = readl_poll_timeout_atomic(base + USB3_TEST_RAMCTRL, val,
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val & USB3_TEST_RAMCTRL_SRAM_INIT_DONE, 1, 10000);
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if (ret)
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return ret;
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writel(USB3_TEST_RSTCTRL_DEASSERT, base + USB3_TEST_RSTCTRL);
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writel(USB3_TEST_RAMCTRL_SRAM_EXT_LD_DONE, base + USB3_TEST_RAMCTRL);
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writel(USB3_TEST_RSTCTRL_RELEASE_OVERRIDE, base + USB3_TEST_RSTCTRL);
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return 0;
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}
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static int rzg3e_phy_usb3_init_helper(void __iomem *base)
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{
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rzg3e_phy_usb2test_phy_init(base);
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return rzg3e_phy_usb3test_phy_init(base);
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}
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static int rzg3e_phy_usb3_init(struct phy *p)
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{
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struct rz_usb3 *r = phy_get_drvdata(p);
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int ret = 0;
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if (!r->skip_reinit)
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ret = rzg3e_phy_usb3_init_helper(r->base);
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return ret;
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}
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static const struct phy_ops rzg3e_phy_usb3_ops = {
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.init = rzg3e_phy_usb3_init,
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.owner = THIS_MODULE,
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};
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static int rzg3e_phy_usb3_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy_provider *provider;
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struct rz_usb3 *r;
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struct phy *phy;
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int ret;
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r = devm_kzalloc(dev, sizeof(*r), GFP_KERNEL);
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if (!r)
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return -ENOMEM;
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r->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(r->base))
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return PTR_ERR(r->base);
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r->rstc = devm_reset_control_get_shared_deasserted(dev, NULL);
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if (IS_ERR(r->rstc))
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return dev_err_probe(dev, PTR_ERR(r->rstc), "failed to get deasserted reset\n");
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/*
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* devm_phy_create() will call pm_runtime_enable(&phy->dev);
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* And then, phy-core will manage runtime pm for this device.
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*/
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ret = devm_pm_runtime_enable(dev);
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if (ret < 0)
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return ret;
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phy = devm_phy_create(dev, NULL, &rzg3e_phy_usb3_ops);
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if (IS_ERR(phy))
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return dev_err_probe(dev, PTR_ERR(phy), "failed to create USB3 PHY\n");
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platform_set_drvdata(pdev, r);
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phy_set_drvdata(phy, r);
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(provider))
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return dev_err_probe(dev, PTR_ERR(provider), "failed to register PHY provider\n");
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return 0;
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}
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static int rzg3e_phy_usb3_suspend(struct device *dev)
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{
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struct rz_usb3 *r = dev_get_drvdata(dev);
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pm_runtime_put(dev);
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reset_control_assert(r->rstc);
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r->skip_reinit = false;
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return 0;
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}
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static int rzg3e_phy_usb3_resume(struct device *dev)
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{
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struct rz_usb3 *r = dev_get_drvdata(dev);
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int ret;
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ret = reset_control_deassert(r->rstc);
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if (ret)
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return ret;
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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goto reset_assert;
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ret = rzg3e_phy_usb3_init_helper(r->base);
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if (ret)
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goto pm_put;
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r->skip_reinit = true;
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return 0;
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pm_put:
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pm_runtime_put(dev);
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reset_assert:
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reset_control_assert(r->rstc);
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return ret;
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}
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static const struct dev_pm_ops rzg3e_phy_usb3_pm = {
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NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3e_phy_usb3_suspend, rzg3e_phy_usb3_resume)
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};
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static const struct of_device_id rzg3e_phy_usb3_match_table[] = {
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{ .compatible = "renesas,r9a09g047-usb3-phy" },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rzg3e_phy_usb3_match_table);
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static struct platform_driver rzg3e_phy_usb3_driver = {
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.driver = {
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.name = "phy_rzg3e_usb3",
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.of_match_table = rzg3e_phy_usb3_match_table,
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.pm = pm_sleep_ptr(&rzg3e_phy_usb3_pm),
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},
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.probe = rzg3e_phy_usb3_probe,
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};
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module_platform_driver(rzg3e_phy_usb3_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Renesas RZ/G3E USB3.0 PHY Driver");
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MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");

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