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Merge branches 'clk-scmi', 'clk-qcom' and 'clk-broadcom' into clk-next
* clk-scmi: clk: scmi: Add duty cycle ops only when duty cycle is supported * clk-qcom: (27 commits) clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC comment clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclk clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc' clk: qcom: gcc: Add support for Global Clock controller found on MSM8937 dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller clk: qcom: Select the intended config in QCS_DISPCC_615 clk: qcom: common: Fix NULL vs IS_ERR() check in qcom_cc_icc_register() clk: qcom: alpha-pll: convert from round_rate() to determine_rate() clk: qcom: milos: Constify 'struct qcom_cc_desc' clk: qcom: gcc: Add support for Global Clock Controller dt-bindings: clock: qcom: document the Glymur Global Clock Controller clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL clk: qcom: rpmh: Add support for Glymur rpmh clocks clk: qcom: Add TCSR clock driver for Glymur SoC dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs clk: qcom: dispcc-glymur: Add support for Display Clock Controller dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs ... * clk-broadcom: clk: bcm: rpi: Maximize V3D clock clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparing clk: bcm: rpi: Add missing logs if firmware fails
4 parents c1e102f + 18db1ff + 575e9a6 + 6526402 commit f0fd248

52 files changed

Lines changed: 13239 additions & 159 deletions

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‎Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -9,16 +9,21 @@ title: Qualcomm Global Clock & Reset Controller on MSM8953
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maintainers:
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- Adam Skladowski <a_skl39@protonmail.com>
1111
- Sireesh Kodali <sireeshkodali@protonmail.com>
12+
- Barnabas Czeman <barnabas.czeman@mainlining.org>
1213

1314
description: |
1415
Qualcomm global clock control module provides the clocks, resets and power
15-
domains on MSM8953.
16+
domains on MSM8937 or MSM8953.
1617
17-
See also: include/dt-bindings/clock/qcom,gcc-msm8953.h
18+
See also::
19+
include/dt-bindings/clock/qcom,gcc-msm8917.h
20+
include/dt-bindings/clock/qcom,gcc-msm8953.h
1821
1922
properties:
2023
compatible:
21-
const: qcom,gcc-msm8953
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enum:
25+
- qcom,gcc-msm8937
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- qcom,gcc-msm8953
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clocks:
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items:

‎Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml‎

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@@ -0,0 +1,98 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm Display Clock & Reset Controller on GLYMUR
8+
9+
maintainers:
10+
- Taniya Das <taniya.das@oss.qualcomm.com>
11+
12+
description: |
13+
Qualcomm display clock control module which supports the clocks, resets and
14+
power domains for the MDSS instances on GLYMUR SoC.
15+
16+
See also:
17+
include/dt-bindings/clock/qcom,dispcc-glymur.h
18+
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properties:
20+
compatible:
21+
enum:
22+
- qcom,glymur-dispcc
23+
24+
clocks:
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items:
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- description: Board CXO clock
27+
- description: Board sleep clock
28+
- description: DisplayPort 0 link clock
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- description: DisplayPort 0 VCO div clock
30+
- description: DisplayPort 1 link clock
31+
- description: DisplayPort 1 VCO div clock
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- description: DisplayPort 2 link clock
33+
- description: DisplayPort 2 VCO div clock
34+
- description: DisplayPort 3 link clock
35+
- description: DisplayPort 3 VCO div clock
36+
- description: DSI 0 PLL byte clock
37+
- description: DSI 0 PLL DSI clock
38+
- description: DSI 1 PLL byte clock
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- description: DSI 1 PLL DSI clock
40+
- description: Standalone PHY 0 PLL link clock
41+
- description: Standalone PHY 0 VCO div clock
42+
- description: Standalone PHY 1 PLL link clock
43+
- description: Standalone PHY 1 VCO div clock
44+
45+
power-domains:
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description:
47+
A phandle and PM domain specifier for the MMCX power domain.
48+
maxItems: 1
49+
50+
required-opps:
51+
description:
52+
A phandle to an OPP node describing required MMCX performance point.
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maxItems: 1
54+
55+
required:
56+
- compatible
57+
- clocks
58+
- power-domains
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
65+
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examples:
67+
- |
68+
#include <dt-bindings/clock/qcom,rpmh.h>
69+
#include <dt-bindings/power/qcom,rpmhpd.h>
70+
71+
clock-controller@af00000 {
72+
compatible = "qcom,glymur-dispcc";
73+
reg = <0x0af00000 0x20000>;
74+
clocks = <&rpmhcc RPMH_CXO_CLK>,
75+
<&sleep_clk>,
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<&mdss_dp_phy0 0>,
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<&mdss_dp_phy0 1>,
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<&mdss_dp_phy1 0>,
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<&mdss_dp_phy1 1>,
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<&mdss_dp_phy2 0>,
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<&mdss_dp_phy2 1>,
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<&mdss_dp_phy3 0>,
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<&mdss_dp_phy3 1>,
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<&mdss_dsi0_phy 0>,
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<&mdss_dsi0_phy 1>,
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<&mdss_dsi1_phy 0>,
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<&mdss_dsi1_phy 1>,
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<&mdss_phy0_link 0>,
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<&mdss_phy0_vco_div 0>,
90+
<&mdss_phy1_link 1>,
91+
<&mdss_phy1_vco_div 1>;
92+
power-domains = <&rpmhpd RPMHPD_MMCX>;
93+
required-opps = <&rpmhpd_opp_low_svs>;
94+
#clock-cells = <1>;
95+
#reset-cells = <1>;
96+
#power-domain-cells = <1>;
97+
};
98+
...

‎Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm Global Clock & Reset Controller on Glymur SoC
8+
9+
maintainers:
10+
- Taniya Das <taniya.das@oss.qualcomm.com>
11+
12+
description: |
13+
Qualcomm global clock control module provides the clocks, resets and power
14+
domains on Glymur SoC.
15+
16+
See also: include/dt-bindings/clock/qcom,glymur-gcc.h
17+
18+
properties:
19+
compatible:
20+
const: qcom,glymur-gcc
21+
22+
clocks:
23+
items:
24+
- description: Board XO source
25+
- description: Board XO_A source
26+
- description: Sleep clock source
27+
- description: USB 0 Phy DP0 GMUX clock source
28+
- description: USB 0 Phy DP1 GMUX clock source
29+
- description: USB 0 Phy PCIE PIPEGMUX clock source
30+
- description: USB 0 Phy PIPEGMUX clock source
31+
- description: USB 0 Phy SYS PCIE PIPEGMUX clock source
32+
- description: USB 1 Phy DP0 GMUX 2 clock source
33+
- description: USB 1 Phy DP1 GMUX 2 clock source
34+
- description: USB 1 Phy PCIE PIPEGMUX clock source
35+
- description: USB 1 Phy PIPEGMUX clock source
36+
- description: USB 1 Phy SYS PCIE PIPEGMUX clock source
37+
- description: USB 2 Phy DP0 GMUX 2 clock source
38+
- description: USB 2 Phy DP1 GMUX 2 clock source
39+
- description: USB 2 Phy PCIE PIPEGMUX clock source
40+
- description: USB 2 Phy PIPEGMUX clock source
41+
- description: USB 2 Phy SYS PCIE PIPEGMUX clock source
42+
- description: PCIe 3a pipe clock
43+
- description: PCIe 3b pipe clock
44+
- description: PCIe 4 pipe clock
45+
- description: PCIe 5 pipe clock
46+
- description: PCIe 6 pipe clock
47+
- description: QUSB4 0 PHY RX 0 clock source
48+
- description: QUSB4 0 PHY RX 1 clock source
49+
- description: QUSB4 1 PHY RX 0 clock source
50+
- description: QUSB4 1 PHY RX 1 clock source
51+
- description: QUSB4 2 PHY RX 0 clock source
52+
- description: QUSB4 2 PHY RX 1 clock source
53+
- description: UFS PHY RX Symbol 0 clock source
54+
- description: UFS PHY RX Symbol 1 clock source
55+
- description: UFS PHY TX Symbol 0 clock source
56+
- description: USB3 PHY 0 pipe clock source
57+
- description: USB3 PHY 1 pipe clock source
58+
- description: USB3 PHY 2 pipe clock source
59+
- description: USB3 UNI PHY pipe 0 clock source
60+
- description: USB3 UNI PHY pipe 1 clock source
61+
- description: USB4 PHY 0 pcie pipe clock source
62+
- description: USB4 PHY 0 Max pipe clock source
63+
- description: USB4 PHY 1 pcie pipe clock source
64+
- description: USB4 PHY 1 Max pipe clock source
65+
- description: USB4 PHY 2 pcie pipe clock source
66+
- description: USB4 PHY 2 Max pipe clock source
67+
68+
required:
69+
- compatible
70+
- clocks
71+
- '#power-domain-cells'
72+
73+
allOf:
74+
- $ref: qcom,gcc.yaml#
75+
76+
unevaluatedProperties: false
77+
78+
examples:
79+
- |
80+
#include <dt-bindings/clock/qcom,rpmh.h>
81+
clock-controller@100000 {
82+
compatible = "qcom,glymur-gcc";
83+
reg = <0x100000 0x1f9000>;
84+
clocks = <&rpmhcc RPMH_CXO_CLK>,
85+
<&rpmhcc RPMH_CXO_CLK_A>,
86+
<&sleep_clk>,
87+
<&usb_0_phy_dp0_gmux>,
88+
<&usb_0_phy_dp1_gmux>,
89+
<&usb_0_phy_pcie_pipegmux>,
90+
<&usb_0_phy_pipegmux>,
91+
<&usb_0_phy_sys_pcie_pipegmux>,
92+
<&usb_1_phy_dp0_gmux_2>,
93+
<&usb_1_phy_dp1_gmux_2>,
94+
<&usb_1_phy_pcie_pipegmux>,
95+
<&usb_1_phy_pipegmux>,
96+
<&usb_1_phy_sys_pcie_pipegmux>,
97+
<&usb_2_phy_dp0_gmux 2>,
98+
<&usb_2_phy_dp1_gmux 2>,
99+
<&usb_2_phy_pcie_pipegmux>,
100+
<&usb_2_phy_pipegmux>,
101+
<&usb_2_phy_sys_pcie_pipegmux>,
102+
<&pcie_3a_pipe>, <&pcie_3b_pipe>,
103+
<&pcie_4_pipe>, <&pcie_5_pipe>,
104+
<&pcie_6_pipe>,
105+
<&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>,
106+
<&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>,
107+
<&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>,
108+
<&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>,
109+
<&ufs_phy_tx_symbol_0>,
110+
<&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>,
111+
<&usb3_phy_2_pipe>,
112+
<&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>,
113+
<&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
114+
<&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
115+
<&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
116+
#clock-cells = <1>;
117+
#reset-cells = <1>;
118+
#power-domain-cells = <1>;
119+
};
120+
121+
...

‎Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm APSS IPQ5424 Clock Controller
8+
9+
maintainers:
10+
- Varadarajan Narayanan <quic_varada@quicinc.com>
11+
12+
description:
13+
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
14+
The RCG and PLL have a separate register space from the GCC.
15+
16+
properties:
17+
compatible:
18+
enum:
19+
- qcom,ipq5424-apss-clk
20+
21+
reg:
22+
maxItems: 1
23+
24+
clocks:
25+
items:
26+
- description: Reference to the XO clock.
27+
- description: Reference to the GPLL0 clock.
28+
29+
'#clock-cells':
30+
const: 1
31+
32+
'#interconnect-cells':
33+
const: 1
34+
35+
required:
36+
- compatible
37+
- reg
38+
- clocks
39+
- '#clock-cells'
40+
- '#interconnect-cells'
41+
42+
additionalProperties: false
43+
44+
examples:
45+
- |
46+
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
47+
48+
apss_clk: clock-controller@fa80000 {
49+
compatible = "qcom,ipq5424-apss-clk";
50+
reg = <0x0fa80000 0x20000>;
51+
clocks = <&xo_board>,
52+
<&gcc GPLL0>;
53+
#clock-cells = <1>;
54+
#interconnect-cells = <1>;
55+
};

‎Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml‎

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1717
properties:
1818
compatible:
1919
enum:
20+
- qcom,glymur-rpmh-clk
2021
- qcom,milos-rpmh-clk
2122
- qcom,qcs615-rpmh-clk
2223
- qcom,qdu1000-rpmh-clk

‎Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml‎

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@@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550
88

99
maintainers:
1010
- Bjorn Andersson <andersson@kernel.org>
11+
- Taniya Das <taniya.das@oss.qualcomm.com>
1112

1213
description: |
1314
Qualcomm TCSR clock control module provides the clocks, resets and
1415
power domains on SM8550
1516
1617
See also:
18+
- include/dt-bindings/clock/qcom,glymur-tcsr.h
1719
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
1820
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
1921
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
@@ -22,6 +24,7 @@ properties:
2224
compatible:
2325
items:
2426
- enum:
27+
- qcom,glymur-tcsr
2528
- qcom,milos-tcsr
2629
- qcom,sar2130p-tcsr
2730
- qcom,sm8550-tcsr

‎Documentation/devicetree/bindings/clock/qcom,videocc.yaml‎

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2323
2424
properties:
2525
compatible:
26-
enum:
27-
- qcom,sc7180-videocc
28-
- qcom,sc7280-videocc
29-
- qcom,sdm845-videocc
30-
- qcom,sm6350-videocc
31-
- qcom,sm8150-videocc
32-
- qcom,sm8250-videocc
26+
oneOf:
27+
- enum:
28+
- qcom,sc7180-videocc
29+
- qcom,sc7280-videocc
30+
- qcom,sdm845-videocc
31+
- qcom,sm6350-videocc
32+
- qcom,sm8150-videocc
33+
- qcom,sm8250-videocc
34+
- items:
35+
- const: qcom,sc8180x-videocc
36+
- const: qcom,sm8150-videocc
3337

3438
clocks:
3539
minItems: 1
@@ -110,8 +114,9 @@ allOf:
110114
- if:
111115
properties:
112116
compatible:
113-
enum:
114-
- qcom,sm8150-videocc
117+
contains:
118+
enum:
119+
- qcom,sm8150-videocc
115120
then:
116121
properties:
117122
clocks:

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