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Jon Linvinodkoul
Jon Lin
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vinodkoul
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phy: rockchip-naneng-combo: Support rk3562
rk3562 has 1 naneng comboPHY used for PCIe and USB3. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250227110836.2343158-2-kever.yang@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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‎drivers/phy/rockchip/phy-rockchip-naneng-combphy.c‎

Lines changed: 152 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -393,6 +393,154 @@ static int rockchip_combphy_probe(struct platform_device *pdev)
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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396+
static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
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{
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const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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unsigned long rate;
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u32 val;
401+
402+
switch (priv->type) {
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case PHY_TYPE_PCIE:
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/* Set SSC downward spread spectrum */
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rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
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PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
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PHYREG32);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
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break;
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case PHY_TYPE_USB3:
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/* Set SSC downward spread spectrum */
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rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
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PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
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PHYREG32);
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/* Enable adaptive CTLE for USB3.0 Rx */
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rockchip_combphy_updatel(priv, PHYREG15_CTLE_EN,
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PHYREG15_CTLE_EN, PHYREG15);
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/* Set PLL KVCO fine tuning signals */
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rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33);
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/* Set PLL LPF R1 to su_trim[10:7]=1001 */
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writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
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/* Set PLL input clock divider 1/2 */
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val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2);
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rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6);
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/* Set PLL loop divider */
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writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
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/* Set PLL KVCO to min and set PLL charge pump current to max */
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writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
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rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
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break;
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default:
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dev_err(priv->dev, "incompatible PHY type\n");
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return -EINVAL;
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}
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rate = clk_get_rate(priv->refclk);
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switch (rate) {
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case REF_CLOCK_24MHz:
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if (priv->type == PHY_TYPE_USB3) {
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/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
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val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE);
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rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
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val, PHYREG15);
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writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
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}
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break;
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case REF_CLOCK_25MHz:
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
465+
break;
466+
case REF_CLOCK_100MHz:
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rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
468+
if (priv->type == PHY_TYPE_PCIE) {
469+
/* PLL KVCO tuning fine */
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val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE);
471+
rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
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val, PHYREG33);
473+
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/* Enable controlling random jitter, aka RMJ */
475+
writel(0x4, priv->mmio + PHYREG12);
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val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
478+
rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
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val, PHYREG6);
480+
481+
writel(0x32, priv->mmio + PHYREG18);
482+
writel(0xf0, priv->mmio + PHYREG11);
483+
}
484+
break;
485+
default:
486+
dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
487+
return -EINVAL;
488+
}
489+
490+
if (priv->ext_refclk) {
491+
rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
492+
if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
493+
val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
494+
val |= PHYREG13_CKRCV_AMP0;
495+
rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
496+
497+
val = readl(priv->mmio + PHYREG14);
498+
val |= PHYREG14_CKRCV_AMP1;
499+
writel(val, priv->mmio + PHYREG14);
500+
}
501+
}
502+
503+
if (priv->enable_ssc) {
504+
val = readl(priv->mmio + PHYREG8);
505+
val |= PHYREG8_SSC_EN;
506+
writel(val, priv->mmio + PHYREG8);
507+
}
508+
509+
return 0;
510+
}
511+
512+
static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
513+
/* pipe-phy-grf */
514+
.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
515+
.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
516+
.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
517+
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
518+
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
519+
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
520+
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
521+
.pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
522+
.pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
523+
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
524+
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
525+
.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
526+
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
527+
.pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
528+
.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
529+
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
530+
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
531+
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
532+
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
533+
};
534+
535+
static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
536+
.num_phys = 1,
537+
.phy_ids = {
538+
0xff750000
539+
},
540+
.grfcfg = &rk3562_combphy_grfcfgs,
541+
.combphy_cfg = rk3562_combphy_cfg,
542+
};
543+
396544
static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
397545
{
398546
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -1046,6 +1194,10 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
10461194
};
10471195

10481196
static const struct of_device_id rockchip_combphy_of_match[] = {
1197+
{
1198+
.compatible = "rockchip,rk3562-naneng-combphy",
1199+
.data = &rk3562_combphy_cfgs,
1200+
},
10491201
{
10501202
.compatible = "rockchip,rk3568-naneng-combphy",
10511203
.data = &rk3568_combphy_cfgs,

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