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Bartosz Golaszewski
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gpio: mlxbf3: use new generic GPIO chip API
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250903-gpio-mmio-gpio-conv-part3-v1-12-ff346509f408@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
1 parent ab61c8b commit f3c19e7

1 file changed

Lines changed: 53 additions & 50 deletions

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‎drivers/gpio/gpio-mlxbf3.c‎

Lines changed: 53 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
#include <linux/device.h>
77
#include <linux/err.h>
88
#include <linux/gpio/driver.h>
9+
#include <linux/gpio/generic.h>
910
#include <linux/interrupt.h>
1011
#include <linux/io.h>
1112
#include <linux/module.h>
@@ -42,7 +43,7 @@
4243
#define MLXBF_GPIO_CLR_ALL_INTS GENMASK(31, 0)
4344

4445
struct mlxbf3_gpio_context {
45-
struct gpio_chip gc;
46+
struct gpio_generic_chip chip;
4647

4748
/* YU GPIO block address */
4849
void __iomem *gpio_set_io;
@@ -58,43 +59,41 @@ static void mlxbf3_gpio_irq_enable(struct irq_data *irqd)
5859
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
5960
struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
6061
irq_hw_number_t offset = irqd_to_hwirq(irqd);
61-
unsigned long flags;
6262
u32 val;
6363

6464
gpiochip_enable_irq(gc, offset);
6565

66-
raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
66+
guard(gpio_generic_lock_irqsave)(&gs->chip);
67+
6768
writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
6869

6970
val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
7071
val |= BIT(offset);
7172
writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
72-
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
7373
}
7474

7575
static void mlxbf3_gpio_irq_disable(struct irq_data *irqd)
7676
{
7777
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
7878
struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
7979
irq_hw_number_t offset = irqd_to_hwirq(irqd);
80-
unsigned long flags;
8180
u32 val;
8281

83-
raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
84-
val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
85-
val &= ~BIT(offset);
86-
writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
82+
scoped_guard(gpio_generic_lock_irqsave, &gs->chip) {
83+
val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
84+
val &= ~BIT(offset);
85+
writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
8786

88-
writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
89-
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
87+
writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
88+
}
9089

9190
gpiochip_disable_irq(gc, offset);
9291
}
9392

9493
static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr)
9594
{
9695
struct mlxbf3_gpio_context *gs = ptr;
97-
struct gpio_chip *gc = &gs->gc;
96+
struct gpio_chip *gc = &gs->chip.gc;
9897
unsigned long pending;
9998
u32 level;
10099

@@ -113,37 +112,33 @@ mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
113112
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
114113
struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
115114
irq_hw_number_t offset = irqd_to_hwirq(irqd);
116-
unsigned long flags;
117115
u32 val;
118116

119-
raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
120-
121-
switch (type & IRQ_TYPE_SENSE_MASK) {
122-
case IRQ_TYPE_EDGE_BOTH:
123-
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
124-
val |= BIT(offset);
125-
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
126-
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
127-
val |= BIT(offset);
128-
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
129-
break;
130-
case IRQ_TYPE_EDGE_RISING:
131-
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
132-
val |= BIT(offset);
133-
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
134-
break;
135-
case IRQ_TYPE_EDGE_FALLING:
136-
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
137-
val |= BIT(offset);
138-
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
139-
break;
140-
default:
141-
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
142-
return -EINVAL;
117+
scoped_guard(gpio_generic_lock_irqsave, &gs->chip) {
118+
switch (type & IRQ_TYPE_SENSE_MASK) {
119+
case IRQ_TYPE_EDGE_BOTH:
120+
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
121+
val |= BIT(offset);
122+
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
123+
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
124+
val |= BIT(offset);
125+
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
126+
break;
127+
case IRQ_TYPE_EDGE_RISING:
128+
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
129+
val |= BIT(offset);
130+
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
131+
break;
132+
case IRQ_TYPE_EDGE_FALLING:
133+
val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
134+
val |= BIT(offset);
135+
writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
136+
break;
137+
default:
138+
return -EINVAL;
139+
}
143140
}
144141

145-
raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
146-
147142
irq_set_handler_locked(irqd, handle_edge_irq);
148143

149144
return 0;
@@ -186,6 +181,7 @@ static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip)
186181

187182
static int mlxbf3_gpio_probe(struct platform_device *pdev)
188183
{
184+
struct gpio_generic_chip_config config;
189185
struct device *dev = &pdev->dev;
190186
struct mlxbf3_gpio_context *gs;
191187
struct gpio_irq_chip *girq;
@@ -211,16 +207,23 @@ static int mlxbf3_gpio_probe(struct platform_device *pdev)
211207
gs->gpio_clr_io = devm_platform_ioremap_resource(pdev, 3);
212208
if (IS_ERR(gs->gpio_clr_io))
213209
return PTR_ERR(gs->gpio_clr_io);
214-
gc = &gs->gc;
215-
216-
ret = bgpio_init(gc, dev, 4,
217-
gs->gpio_io + MLXBF_GPIO_READ_DATA_IN,
218-
gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET,
219-
gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR,
220-
gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET,
221-
gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0);
210+
gc = &gs->chip.gc;
211+
212+
config = (typeof(config)){
213+
.dev = dev,
214+
.sz = 4,
215+
.dat = gs->gpio_io + MLXBF_GPIO_READ_DATA_IN,
216+
.set = gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET,
217+
.clr = gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR,
218+
.dirout = gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET,
219+
.dirin = gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR,
220+
};
221+
222+
ret = gpio_generic_chip_init(&gs->chip, &config);
222223
if (ret)
223-
return dev_err_probe(dev, ret, "%s: bgpio_init() failed", __func__);
224+
return dev_err_probe(dev, ret,
225+
"%s: failed to initialize the generic GPIO chip",
226+
__func__);
224227

225228
gc->request = gpiochip_generic_request;
226229
gc->free = gpiochip_generic_free;
@@ -229,7 +232,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pdev)
229232

230233
irq = platform_get_irq_optional(pdev, 0);
231234
if (irq >= 0) {
232-
girq = &gs->gc.irq;
235+
girq = &gs->chip.gc.irq;
233236
gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip);
234237
girq->default_type = IRQ_TYPE_NONE;
235238
/* This will let us handle the parent IRQ in the driver */
@@ -250,7 +253,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pdev)
250253

251254
platform_set_drvdata(pdev, gs);
252255

253-
ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
256+
ret = devm_gpiochip_add_data(dev, gc, gs);
254257
if (ret)
255258
dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n");
256259

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