Skip to content

Commit f8e0f4c

Browse files
mattropemattrope
committed
drm/xe: Track maximum GTs per tile on a per-platform basis
Today all of our platforms fall into one of three cases: * Single tile platforms with a single (primary) GT * Single tile platforms with two GTs (primary + media) * Two-tile platforms with a single GT (primary) in each Our numbering of GTs has been a bit inconsistent between platforms (e.g., GT1 is the media GT on some platforms, but the second tile's primary GT on others). In the future we'll likely have platforms that are both multi-tile and multi-GT, which will make the situation more confusing. We could also wind up with more than just two types of GTs at some point in the future. Going forward we should standardize the way we assign uapi GT IDs to internal GT structures. Let's declare that for userspace GT ID n, GT[n]'s tile = n / (max gt per tile) GT[n]'s slot within tile = n % (max gt per tile) We don't want the GT numbering to change for any of our current platforms since the current IDs are part of our ABI contract with userspace so this means we should track the 'max gt per tile' value on a per-platform basis rather than just using a single value across the driver. Encode this into device descriptors in xe_pci.c and use the per-platform number for various checks in the code. Constant XE_MAX_GT_PER_TILE will remain just as the maximum across all platforms for easy of sizing array allocations. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20250701201320.2514369-12-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
1 parent 0fc957c commit f8e0f4c

4 files changed

Lines changed: 41 additions & 24 deletions

File tree

‎drivers/gpu/drm/xe/xe_device.h‎

Lines changed: 20 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -60,35 +60,32 @@ static inline struct xe_tile *xe_device_get_root_tile(struct xe_device *xe)
6060
return &xe->tiles[0];
6161
}
6262

63+
/*
64+
* Highest GT/tile count for any platform. Used only for memory allocation
65+
* sizing. Any logic looping over GTs or mapping userspace GT IDs into GT
66+
* structures should use the per-platform xe->info.max_gt_per_tile instead.
67+
*/
6368
#define XE_MAX_GT_PER_TILE 2
6469

65-
static inline struct xe_gt *xe_tile_get_gt(struct xe_tile *tile, u8 gt_id)
66-
{
67-
if (drm_WARN_ON(&tile_to_xe(tile)->drm, gt_id >= XE_MAX_GT_PER_TILE))
68-
gt_id = 0;
69-
70-
return gt_id ? tile->media_gt : tile->primary_gt;
71-
}
72-
7370
static inline struct xe_gt *xe_device_get_gt(struct xe_device *xe, u8 gt_id)
7471
{
75-
struct xe_tile *root_tile = xe_device_get_root_tile(xe);
72+
struct xe_tile *tile;
7673
struct xe_gt *gt;
7774

78-
/*
79-
* FIXME: This only works for now because multi-tile and standalone
80-
* media are mutually exclusive on the platforms we have today.
81-
*
82-
* id => GT mapping may change once we settle on how we want to handle
83-
* our UAPI.
84-
*/
85-
if (MEDIA_VER(xe) >= 13) {
86-
gt = xe_tile_get_gt(root_tile, gt_id);
87-
} else {
88-
if (drm_WARN_ON(&xe->drm, gt_id >= XE_MAX_TILES_PER_DEVICE))
89-
gt_id = 0;
90-
91-
gt = xe->tiles[gt_id].primary_gt;
75+
if (gt_id >= xe->info.tile_count * xe->info.max_gt_per_tile)
76+
return NULL;
77+
78+
tile = &xe->tiles[gt_id / xe->info.max_gt_per_tile];
79+
switch (gt_id % xe->info.max_gt_per_tile) {
80+
default:
81+
xe_assert(xe, false);
82+
fallthrough;
83+
case 0:
84+
gt = tile->primary_gt;
85+
break;
86+
case 1:
87+
gt = tile->media_gt;
88+
break;
9289
}
9390

9491
if (!gt)

‎drivers/gpu/drm/xe/xe_device_types.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -294,6 +294,8 @@ struct xe_device {
294294
u8 vram_flags;
295295
/** @info.tile_count: Number of tiles */
296296
u8 tile_count;
297+
/** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */
298+
u8 max_gt_per_tile;
297299
/** @info.gt_count: Total number of GTs for entire device */
298300
u8 gt_count;
299301
/** @info.vm_max_level: Max VM level */

‎drivers/gpu/drm/xe/xe_pci.c‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ struct xe_device_desc {
5757

5858
u8 dma_mask_size;
5959
u8 max_remote_tiles:2;
60+
u8 max_gt_per_tile:2;
6061

6162
u8 require_force_probe:1;
6263
u8 is_dgfx:1;
@@ -208,6 +209,7 @@ static const struct xe_device_desc tgl_desc = {
208209
.dma_mask_size = 39,
209210
.has_display = true,
210211
.has_llc = true,
212+
.max_gt_per_tile = 1,
211213
.require_force_probe = true,
212214
};
213215

@@ -218,6 +220,7 @@ static const struct xe_device_desc rkl_desc = {
218220
.dma_mask_size = 39,
219221
.has_display = true,
220222
.has_llc = true,
223+
.max_gt_per_tile = 1,
221224
.require_force_probe = true,
222225
};
223226

@@ -230,6 +233,7 @@ static const struct xe_device_desc adl_s_desc = {
230233
.dma_mask_size = 39,
231234
.has_display = true,
232235
.has_llc = true,
236+
.max_gt_per_tile = 1,
233237
.require_force_probe = true,
234238
.subplatforms = (const struct xe_subplatform_desc[]) {
235239
{ XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
@@ -246,6 +250,7 @@ static const struct xe_device_desc adl_p_desc = {
246250
.dma_mask_size = 39,
247251
.has_display = true,
248252
.has_llc = true,
253+
.max_gt_per_tile = 1,
249254
.require_force_probe = true,
250255
.subplatforms = (const struct xe_subplatform_desc[]) {
251256
{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
@@ -260,6 +265,7 @@ static const struct xe_device_desc adl_n_desc = {
260265
.dma_mask_size = 39,
261266
.has_display = true,
262267
.has_llc = true,
268+
.max_gt_per_tile = 1,
263269
.require_force_probe = true,
264270
};
265271

@@ -275,6 +281,7 @@ static const struct xe_device_desc dg1_desc = {
275281
.has_display = true,
276282
.has_gsc_nvm = 1,
277283
.has_heci_gscfi = 1,
284+
.max_gt_per_tile = 1,
278285
.require_force_probe = true,
279286
};
280287

@@ -298,6 +305,7 @@ static const struct xe_device_desc ats_m_desc = {
298305
.pre_gmdid_graphics_ip = &graphics_ip_xehpg,
299306
.pre_gmdid_media_ip = &media_ip_xehpm,
300307
.dma_mask_size = 46,
308+
.max_gt_per_tile = 1,
301309
.require_force_probe = true,
302310

303311
DG2_FEATURES,
@@ -308,6 +316,7 @@ static const struct xe_device_desc dg2_desc = {
308316
.pre_gmdid_graphics_ip = &graphics_ip_xehpg,
309317
.pre_gmdid_media_ip = &media_ip_xehpm,
310318
.dma_mask_size = 46,
319+
.max_gt_per_tile = 1,
311320
.require_force_probe = true,
312321

313322
DG2_FEATURES,
@@ -324,6 +333,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
324333
.has_display = false,
325334
.has_gsc_nvm = 1,
326335
.has_heci_gscfi = 1,
336+
.max_gt_per_tile = 1,
327337
.max_remote_tiles = 1,
328338
.require_force_probe = true,
329339
.has_mbx_power_limits = false,
@@ -336,13 +346,15 @@ static const struct xe_device_desc mtl_desc = {
336346
.dma_mask_size = 46,
337347
.has_display = true,
338348
.has_pxp = true,
349+
.max_gt_per_tile = 2,
339350
};
340351

341352
static const struct xe_device_desc lnl_desc = {
342353
PLATFORM(LUNARLAKE),
343354
.dma_mask_size = 46,
344355
.has_display = true,
345356
.has_pxp = true,
357+
.max_gt_per_tile = 2,
346358
.needs_scratch = true,
347359
};
348360

@@ -355,6 +367,7 @@ static const struct xe_device_desc bmg_desc = {
355367
.has_mbx_power_limits = true,
356368
.has_gsc_nvm = 1,
357369
.has_heci_cscfi = 1,
370+
.max_gt_per_tile = 2,
358371
.needs_scratch = true,
359372
};
360373

@@ -363,6 +376,7 @@ static const struct xe_device_desc ptl_desc = {
363376
.dma_mask_size = 46,
364377
.has_display = true,
365378
.has_sriov = true,
379+
.max_gt_per_tile = 2,
366380
.require_force_probe = true,
367381
.needs_scratch = true,
368382
};
@@ -611,6 +625,10 @@ static int xe_info_init_early(struct xe_device *xe,
611625
xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
612626
xe_modparam.probe_display &&
613627
desc->has_display;
628+
629+
xe_assert(xe, desc->max_gt_per_tile > 0);
630+
xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE);
631+
xe->info.max_gt_per_tile = desc->max_gt_per_tile;
614632
xe->info.tile_count = 1 + desc->max_remote_tiles;
615633

616634
err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0);

‎drivers/gpu/drm/xe/xe_query.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ query_engine_cycles(struct xe_device *xe,
141141
return -EINVAL;
142142

143143
eci = &resp.eci;
144-
if (eci->gt_id >= XE_MAX_GT_PER_TILE)
144+
if (eci->gt_id >= xe->info.max_gt_per_tile)
145145
return -EINVAL;
146146

147147
gt = xe_device_get_gt(xe, eci->gt_id);

0 commit comments

Comments
 (0)