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marcanjannau
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ASoC: tas2764: Set the SDOUT polarity correctly
TX launch polarity needs to be the opposite of RX capture polarity, to generate the right bit slot alignment. Signed-off-by: Hector Martin <marcan@marcan.st>
1 parent 924e770 commit fbe64b0

2 files changed

Lines changed: 15 additions & 1 deletion

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sound/soc/codecs/tas2764.c

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -409,7 +409,7 @@ static int tas2764_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
409409
{
410410
struct snd_soc_component *component = dai->component;
411411
struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
412-
u8 tdm_rx_start_slot = 0, asi_cfg_0 = 0, asi_cfg_1 = 0;
412+
u8 tdm_rx_start_slot = 0, asi_cfg_0 = 0, asi_cfg_1 = 0, asi_cfg_4 = 0;
413413
int ret;
414414

415415
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
@@ -418,12 +418,14 @@ static int tas2764_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
418418
fallthrough;
419419
case SND_SOC_DAIFMT_NB_NF:
420420
asi_cfg_1 = TAS2764_TDM_CFG1_RX_RISING;
421+
asi_cfg_4 = TAS2764_TDM_CFG4_TX_FALLING;
421422
break;
422423
case SND_SOC_DAIFMT_IB_IF:
423424
asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START;
424425
fallthrough;
425426
case SND_SOC_DAIFMT_IB_NF:
426427
asi_cfg_1 = TAS2764_TDM_CFG1_RX_FALLING;
428+
asi_cfg_4 = TAS2764_TDM_CFG4_TX_RISING;
427429
break;
428430
}
429431

@@ -433,6 +435,12 @@ static int tas2764_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
433435
if (ret < 0)
434436
return ret;
435437

438+
ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG4,
439+
TAS2764_TDM_CFG4_TX_MASK,
440+
asi_cfg_4);
441+
if (ret < 0)
442+
return ret;
443+
436444
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
437445
case SND_SOC_DAIFMT_I2S:
438446
asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START;

sound/soc/codecs/tas2764.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,12 @@
8484
#define TAS2764_TDM_CFG3_RXS_SHIFT 0x4
8585
#define TAS2764_TDM_CFG3_MASK GENMASK(3, 0)
8686

87+
/* TDM Configuration Reg4 */
88+
#define TAS2764_TDM_CFG4 TAS2764_REG(0X0, 0x0c)
89+
#define TAS2764_TDM_CFG4_TX_MASK BIT(0)
90+
#define TAS2764_TDM_CFG4_TX_RISING 0x0
91+
#define TAS2764_TDM_CFG4_TX_FALLING BIT(0)
92+
8793
/* TDM Configuration Reg5 */
8894
#define TAS2764_TDM_CFG5 TAS2764_REG(0X0, 0x0e)
8995
#define TAS2764_TDM_CFG5_VSNS_MASK BIT(6)

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