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asdfugiljannau
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tty: serial: samsung: Fix serial rx on Apple A7-A9
Apple's older A7-A9 SoCs seems to use bit 3 in UTRSTAT as RXTO, which is enabled by bit 11 in UCON. Access these bits in addition to the original RXTO and RXTO enable bits, to allow serial rx to function on A7-A9 SoCs. This change does not appear to affect the A10 SoC and up. Signed-off-by: Nick Chan <towinchenmi@gmail.com>
1 parent 3a78f7f commit fd386f5

2 files changed

Lines changed: 23 additions & 12 deletions

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drivers/tty/serial/samsung_tty.c

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -550,6 +550,7 @@ static void s3c24xx_serial_stop_rx(struct uart_port *port)
550550
case TYPE_APPLE_S5L:
551551
s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
552552
s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
553+
s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON);
553554
break;
554555
default:
555556
disable_irq_nosync(ourport->rx_irq);
@@ -968,9 +969,11 @@ static irqreturn_t apple_serial_handle_irq(int irq, void *id)
968969
u32 pend = rd_regl(port, S3C2410_UTRSTAT);
969970
irqreturn_t ret = IRQ_NONE;
970971

971-
if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
972+
if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO |
973+
APPLE_S5L_UTRSTAT_RXTO_LEGACY)) {
972974
wr_regl(port, S3C2410_UTRSTAT,
973-
APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
975+
APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO |
976+
APPLE_S5L_UTRSTAT_RXTO_LEGACY);
974977
ret = s3c24xx_serial_rx_irq(irq, id);
975978
}
976979
if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
@@ -1195,7 +1198,8 @@ static void apple_s5l_serial_shutdown(struct uart_port *port)
11951198
ucon = rd_regl(port, S3C2410_UCON);
11961199
ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
11971200
APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1198-
APPLE_S5L_UCON_RXTO_ENA_MSK);
1201+
APPLE_S5L_UCON_RXTO_ENA_MSK |
1202+
APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK);
11991203
wr_regl(port, S3C2410_UCON, ucon);
12001204

12011205
wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
@@ -1292,6 +1296,7 @@ static int apple_s5l_serial_startup(struct uart_port *port)
12921296
/* Enable Rx Interrupt */
12931297
s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
12941298
s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1299+
s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON);
12951300

12961301
return ret;
12971302
}
@@ -2148,13 +2153,15 @@ static int s3c24xx_serial_resume_noirq(struct device *dev)
21482153

21492154
ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
21502155
APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2151-
APPLE_S5L_UCON_RXTO_ENA_MSK);
2156+
APPLE_S5L_UCON_RXTO_ENA_MSK |
2157+
APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK);
21522158

21532159
if (ourport->tx_enabled)
21542160
ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
21552161
if (ourport->rx_enabled)
21562162
ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2157-
APPLE_S5L_UCON_RXTO_ENA_MSK;
2163+
APPLE_S5L_UCON_RXTO_ENA_MSK |
2164+
APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK;
21582165

21592166
wr_regl(port, S3C2410_UCON, ucon);
21602167

include/linux/serial_s3c.h

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -246,24 +246,28 @@
246246
S5PV210_UFCON_TXTRIG4 | \
247247
S5PV210_UFCON_RXTRIG4)
248248

249-
#define APPLE_S5L_UCON_RXTO_ENA 9
250-
#define APPLE_S5L_UCON_RXTHRESH_ENA 12
251-
#define APPLE_S5L_UCON_TXTHRESH_ENA 13
252-
#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA)
253-
#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA)
254-
#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA)
249+
#define APPLE_S5L_UCON_RXTO_ENA 9
250+
#define APPLE_S5L_UCON_RXTO_LEGACY_ENA 11
251+
#define APPLE_S5L_UCON_RXTHRESH_ENA 12
252+
#define APPLE_S5L_UCON_TXTHRESH_ENA 13
253+
#define APPLE_S5L_UCON_RXTO_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_ENA)
254+
#define APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK BIT(APPLE_S5L_UCON_RXTO_LEGACY_ENA)
255+
#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_RXTHRESH_ENA)
256+
#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK BIT(APPLE_S5L_UCON_TXTHRESH_ENA)
255257

256258
#define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \
257259
S3C2410_UCON_RXIRQMODE | \
258260
S3C2410_UCON_RXFIFO_TOI)
259261
#define APPLE_S5L_UCON_MASK (APPLE_S5L_UCON_RXTO_ENA_MSK | \
262+
APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK | \
260263
APPLE_S5L_UCON_RXTHRESH_ENA_MSK | \
261264
APPLE_S5L_UCON_TXTHRESH_ENA_MSK)
262265

266+
#define APPLE_S5L_UTRSTAT_RXTO_LEGACY BIT(3)
263267
#define APPLE_S5L_UTRSTAT_RXTHRESH BIT(4)
264268
#define APPLE_S5L_UTRSTAT_TXTHRESH BIT(5)
265269
#define APPLE_S5L_UTRSTAT_RXTO BIT(9)
266-
#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0)
270+
#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f8)
267271

268272
#ifndef __ASSEMBLY__
269273

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