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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Will Deacon: "There's good stuff across the board, including some nice mm improvements for CPUs with the 'noabort' BBML2 feature and a clever patch to allow ptdump to play nicely with block mappings in the vmalloc area. Confidential computing: - Add support for accepting secrets from firmware (e.g. ACPI CCEL) and mapping them with appropriate attributes. CPU features: - Advertise atomic floating-point instructions to userspace - Extend Spectre workarounds to cover additional Arm CPU variants - Extend list of CPUs that support break-before-make level 2 and guarantee not to generate TLB conflict aborts for changes of mapping granularity (BBML2_NOABORT) - Add GCS support to our uprobes implementation. Documentation: - Remove bogus SME documentation concerning register state when entering/exiting streaming mode. Entry code: - Switch over to the generic IRQ entry code (GENERIC_IRQ_ENTRY) - Micro-optimise syscall entry path with a compiler branch hint. Memory management: - Enable huge mappings in vmalloc space even when kernel page-table dumping is enabled - Tidy up the types used in our early MMU setup code - Rework rodata= for closer parity with the behaviour on x86 - For CPUs implementing BBML2_NOABORT, utilise block mappings in the linear map even when rodata= applies to virtual aliases - Don't re-allocate the virtual region between '_text' and '_stext', as doing so confused tools parsing /proc/vmcore. Miscellaneous: - Clean-up Kconfig menuconfig text for architecture features - Avoid redundant bitmap_empty() during determination of supported SME vector lengths - Re-enable warnings when building the 32-bit vDSO object - Avoid breaking our eggs at the wrong end. Perf and PMUs: - Support for v3 of the Hisilicon L3C PMU - Support for Hisilicon's MN and NoC PMUs - Support for Fujitsu's Uncore PMU - Support for SPE's extended event filtering feature - Preparatory work to enable data source filtering in SPE - Support for multiple lanes in the DWC PCIe PMU - Support for i.MX94 in the IMX DDR PMU driver - MAINTAINERS update (Thank you, Yicong) - Minor driver fixes (PERF_IDX2OFF() overflow, CMN register offsets). Selftests: - Add basic LSFE check to the existing hwcaps test - Support nolibc in GCS tests - Extend SVE ptrace test to pass unsupported regsets and invalid vector lengths - Minor cleanups (typos, cosmetic changes). System registers: - Fix ID_PFR1_EL1 definition - Fix incorrect signedness of some fields in ID_AA64MMFR4_EL1 - Sync TCR_EL1 definition with the latest Arm ARM (L.b) - Be stricter about the input fed into our AWK sysreg generator script - Typo fixes and removal of redundant definitions. ACPI, EFI and PSCI: - Decouple Arm's "Software Delegated Exception Interface" (SDEI) support from the ACPI GHES code so that it can be used by platforms booted with device-tree - Remove unnecessary per-CPU tracking of the FPSIMD state across EFI runtime calls - Fix a node refcount imbalance in the PSCI device-tree code. CPU Features: - Ensure register sanitisation is applied to fields in ID_AA64MMFR4 - Expose AIDR_EL1 to userspace via sysfs, primarily so that KVM guests can reliably query the underlying CPU types from the VMM - Re-enabling of SME support (CONFIG_ARM64_SME) as a result of fixes to our context-switching, signal handling and ptrace code" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (93 commits) arm64: cpufeature: Remove duplicate asm/mmu.h header arm64: Kconfig: Make CPU_BIG_ENDIAN depend on BROKEN perf/dwc_pcie: Fix use of uninitialized variable arm/syscalls: mark syscall invocation as likely in invoke_syscall Documentation: hisi-pmu: Add introduction to HiSilicon V3 PMU Documentation: hisi-pmu: Fix of minor format error drivers/perf: hisi: Add support for L3C PMU v3 drivers/perf: hisi: Refactor the event configuration of L3C PMU drivers/perf: hisi: Extend the field of tt_core drivers/perf: hisi: Extract the event filter check of L3C PMU drivers/perf: hisi: Simplify the probe process of each L3C PMU version drivers/perf: hisi: Export hisi_uncore_pmu_isr() drivers/perf: hisi: Relax the event ID check in the framework perf: Fujitsu: Add the Uncore PMU driver arm64: map [_text, _stext) virtual address range non-executable+read-only arm64/sysreg: Update TCR_EL1 register arm64: Enable vmalloc-huge with ptdump arm64: cpufeature: add Neoverse-V3AE to BBML2 allow list arm64: errata: Apply workarounds for Neoverse-V3AE arm64: cputype: Add Neoverse-V3AE definitions ...
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‎Documentation/admin-guide/kernel-parameters.txt‎

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rodata= [KNL,EARLY]
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on Mark read-only kernel memory as read-only (default).
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off Leave read-only kernel memory writable for debugging.
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full Mark read-only kernel memory and aliases as read-only
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[arm64]
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noalias Mark read-only kernel memory as read-only but retain
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writable aliases in the direct map for regions outside
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of the kernel image. [arm64]
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rockchip.usb_uart
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[EARLY]

‎Documentation/admin-guide/perf/dwc_pcie_pmu.rst‎

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- one 64-bit counter for Time Based Analysis (RX/TX data throughput and
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time spent in each low-power LTSSM state) and
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- one 32-bit counter for Event Counting (error and non-error events for
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a specified lane)
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- one 32-bit counter per event for Event Counting (error and non-error
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events for a specified lane)
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Note: There is no interrupt for counter overflow.
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‎Documentation/admin-guide/perf/fujitsu_uncore_pmu.rst‎

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.. SPDX-License-Identifier: GPL-2.0-only
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================================================
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Fujitsu Uncore Performance Monitoring Unit (PMU)
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================================================
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This driver supports the Uncore MAC PMUs and the Uncore PCI PMUs found
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in Fujitsu chips.
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Each MAC PMU on these chips is exposed as a uncore perf PMU with device name
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mac_iod<iod>_mac<mac>_ch<ch>.
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And each PCI PMU on these chips is exposed as a uncore perf PMU with device name
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pci_iod<iod>_pci<pci>.
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The driver provides a description of its available events and configuration
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options in sysfs, see /sys/bus/event_sources/devices/mac_iod<iod>_mac<mac>_ch<ch>/
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and /sys/bus/event_sources/devices/pci_iod<iod>_pci<pci>/.
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This driver exports:
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- formats, used by perf user space and other tools to configure events
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- events, used by perf user space and other tools to create events
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symbolically, e.g.:
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perf stat -a -e mac_iod0_mac0_ch0/event=0x21/ ls
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perf stat -a -e pci_iod0_pci0/event=0x24/ ls
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- cpumask, used by perf user space and other tools to know on which CPUs
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to open the events
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This driver supports the following events for MAC:
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- cycles
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This event counts MAC cycles at MAC frequency.
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- read-count
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This event counts the number of read requests to MAC.
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- read-count-request
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This event counts the number of read requests including retry to MAC.
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- read-count-return
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This event counts the number of responses to read requests to MAC.
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- read-count-request-pftgt
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This event counts the number of read requests including retry with PFTGT
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flag.
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- read-count-request-normal
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This event counts the number of read requests including retry without PFTGT
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flag.
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- read-count-return-pftgt-hit
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This event counts the number of responses to read requests which hit the
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PFTGT buffer.
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- read-count-return-pftgt-miss
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This event counts the number of responses to read requests which miss the
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PFTGT buffer.
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- read-wait
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This event counts outstanding read requests issued by DDR memory controller
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per cycle.
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- write-count
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This event counts the number of write requests to MAC (including zero write,
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full write, partial write, write cancel).
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- write-count-write
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This event counts the number of full write requests to MAC (not including
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zero write).
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- write-count-pwrite
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This event counts the number of partial write requests to MAC.
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- memory-read-count
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This event counts the number of read requests from MAC to memory.
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- memory-write-count
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This event counts the number of full write requests from MAC to memory.
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- memory-pwrite-count
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This event counts the number of partial write requests from MAC to memory.
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- ea-mac
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This event counts energy consumption of MAC.
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- ea-memory
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This event counts energy consumption of memory.
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- ea-memory-mac-write
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This event counts the number of write requests from MAC to memory.
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- ea-ha
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This event counts energy consumption of HA.
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'ea' is the abbreviation for 'Energy Analyzer'.
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Examples for use with perf::
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perf stat -e mac_iod0_mac0_ch0/ea-mac/ ls
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And, this driver supports the following events for PCI:
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- pci-port0-cycles
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This event counts PCI cycles at PCI frequency in port0.
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- pci-port0-read-count
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This event counts read transactions for data transfer in port0.
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- pci-port0-read-count-bus
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This event counts read transactions for bus usage in port0.
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- pci-port0-write-count
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This event counts write transactions for data transfer in port0.
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- pci-port0-write-count-bus
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This event counts write transactions for bus usage in port0.
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- pci-port1-cycles
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This event counts PCI cycles at PCI frequency in port1.
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- pci-port1-read-count
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This event counts read transactions for data transfer in port1.
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- pci-port1-read-count-bus
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This event counts read transactions for bus usage in port1.
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- pci-port1-write-count
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This event counts write transactions for data transfer in port1.
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- pci-port1-write-count-bus
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This event counts write transactions for bus usage in port1.
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- ea-pci
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This event counts energy consumption of PCI.
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'ea' is the abbreviation for 'Energy Analyzer'.
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Examples for use with perf::
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perf stat -e pci_iod0_pci0/ea-pci/ ls
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Given that these are uncore PMUs the driver does not support sampling, therefore
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"perf record" will not work. Per-task perf sessions are not supported.

‎Documentation/admin-guide/perf/hisi-pmu.rst‎

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Each device PMU has separate registers for event counting, control and
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interrupt, and the PMU driver shall register perf PMU drivers like L3C,
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HHA and DDRC etc. The available events and configuration options shall
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be described in the sysfs, see:
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be described in the sysfs, see::
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/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>
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/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
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The "perf list" command shall list the available events from sysfs.
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Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
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- 2'b00: default value, count the events which sent to the both uring and
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uring_ext channel;
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6. ch: NoC PMU supports filtering the event counts of certain transaction
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channel with this option. The current supported channels are as follows:
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- 3'b010: Request channel
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- 3'b100: Snoop channel
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- 3'b110: Response channel
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- 3'b111: Data channel
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7. tt_en: NoC PMU supports counting only transactions that have tracetag set
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if this option is set. See the 2nd list for more information about tracetag.
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For HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are
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further divided into parts for finer granularity of tracing, each part has its
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own dedicated PMU, and all such PMUs together cover the monitoring job of events
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on particular uncore device. Such PMUs are described in sysfs with name format
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slightly changed::
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/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}_{Z}/ddrc{Y}_{Z}/noc{Y}_{Z}>
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Z is the sub-id, indicating different PMUs for part of hardware device.
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Usage of most PMUs with different sub-ids are identical. Specially, L3C PMU
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provides ``ext`` option to allow exploration of even finer granual statistics
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of L3C PMU. L3C PMU driver uses that as hint of termination when delivering
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perf command to hardware:
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- ext=0: Default, could be used with event names.
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- ext=1 and ext=2: Must be used with event codes, event names are not supported.
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An example of perf command could be::
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$# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5
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or::
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$# perf stat -a -e hisi_sccl0_l3c1_0/event=0x1,ext=1/ sleep 5
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As above, ``hisi_sccl0_l3c1_0`` locates PMU of Super CPU CLuster 0, L3 cache 1
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pipe0.
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First command locates the first part of L3C since ``ext=0`` is implied by
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default. Second command issues the counting on another part of L3C with the
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event ``0x1``.
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Users could configure IDs to count data come from specific CCL/ICL, by setting
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srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting
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tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not

‎Documentation/admin-guide/perf/index.rst‎

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cxl
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ampere_cspmu
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mrvl-pem-pmu
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fujitsu_uncore_pmu

‎Documentation/arch/arm64/booting.rst‎

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- HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
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- HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
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For CPUs with SPE data source filtering (FEAT_SPE_FDS):
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- If EL3 is present:
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- MDCR_EL3.EnPMS3 (bit 42) must be initialised to 0b1.
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- If the kernel is entered at EL1 and EL2 is present:
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- HDFGRTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1.
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- HDFGWTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1.
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For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS):
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- If the kernel is entered at EL1 and EL2 is present:

‎Documentation/arch/arm64/elf_hwcaps.rst‎

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HWCAP3_MTE_STORE_ONLY
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Functionality implied by ID_AA64PFR2_EL1.MTESTOREONLY == 0b0001.
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HWCAP3_LSFE
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Functionality implied by ID_AA64ISAR3_EL1.LSFE == 0b0001
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4. Unused AT_HWCAP bits
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-----------------------
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‎Documentation/arch/arm64/silicon-errata.rst‎

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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V3AE | #3312417 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | MMU-500 | #841119,826419 | ARM_SMMU_MMU_500_CPRE_ERRATA|
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| | | #562869,1047329 | |
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+----------------+-----------------+-----------------+-----------------------------+

‎Documentation/arch/arm64/sme.rst‎

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mode SVE vector.
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3. Sharing of streaming and non-streaming mode SVE state
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---------------------------------------------------------
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It is implementation defined which if any parts of the SVE state are shared
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between streaming and non-streaming modes. When switching between modes
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via software interfaces such as ptrace if no register content is provided as
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part of switching no state will be assumed to be shared and everything will
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be zeroed.
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4. System call behaviour
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3. System call behaviour
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exceptions for execve() described in section 6.
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5. Signal handling
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4. Signal handling
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* Signal handlers are invoked with PSTATE.SM=0, PSTATE.ZA=0, and TPIDR2_EL0=0.

‎Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml‎

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- items:
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- enum:
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- fsl,imx94-ddr-pmu
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- fsl,imx95-ddr-pmu
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- const: fsl,imx93-ddr-pmu
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