PCI: apple: Skip controller port setup for online links

U-boot gained recently support for PCIe controller on Apple silicon
devices. It is currently unkown how to reset / retrain already brought
up ports. Redoing the controller level setup breaks the links.
Check the link status before performing controller level port/link
setup.

Link: https://lore.kernel.org/u-boot/20230121192800.82428-1-kettenis@openbsd.org/
Signed-off-by: Janne Grunau <j@jannau.net>

Author: jannau

drivers/pci/controller/pcie-apple.c

@@ -605,15 +605,13 @@ static int apple_pcie_probe_port(struct device_node *np)
 	return 0;
 }
 
-static int apple_pcie_setup_port(struct apple_pcie *pcie,
+static int apple_pcie_setup_link(struct apple_pcie *pcie,
+				 struct apple_pcie_port *port,
 				 struct device_node *np)
 {
-	struct platform_device *platform = to_platform_device(pcie->dev);
-	struct apple_pcie_port *port;
-	struct gpio_desc *reset, *pwren = NULL;
-	u32 stat, idx;
-	int ret, i;
-	char name[16];
+	struct gpio_desc *reset, *pwren;
+	u32 stat;
+	int ret;
 
 	reset = devm_fwnode_gpiod_get(pcie->dev, of_fwnode_handle(np), "reset",
 				      GPIOD_OUT_LOW, "PERST#");
@@ -629,32 +627,6 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie,
 			return PTR_ERR(pwren);
 	}
 
-	port = devm_kzalloc(pcie->dev, sizeof(*port), GFP_KERNEL);
-	if (!port)
-		return -ENOMEM;
-
-	ret = of_property_read_u32_index(np, "reg", 0, &idx);
-	if (ret)
-		return ret;
-
-	/* Use the first reg entry to work out the port index */
-	port->idx = idx >> 11;
-	port->pcie = pcie;
-	port->np = np;
-
-	snprintf(name, sizeof(name), "port%d", port->idx);
-	port->base = devm_platform_ioremap_resource_byname(platform, name);
-	if (IS_ERR(port->base))
-		port->base = devm_platform_ioremap_resource(platform, port->idx + 2);
-	if (IS_ERR(port->base)) {
-		return PTR_ERR(port->base);
-	}
-
-	snprintf(name, sizeof(name), "phy%d", port->idx);
-	port->phy = devm_platform_ioremap_resource_byname(platform, name);
-	if (IS_ERR(port->phy))
-		port->phy = pcie->base + CORE_PHY_DEFAULT_BASE(port->idx);
-
 	rmw_set(PORT_APPCLK_EN, port->base + PORT_APPCLK);
 
 	/* Assert PERST# before setting up the clock */
@@ -690,6 +662,52 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie,
 		return ret;
 	}
 
+	return 0;
+}
+
+static int apple_pcie_setup_port(struct apple_pcie *pcie,
+				 struct device_node *np)
+{
+	struct platform_device *platform = to_platform_device(pcie->dev);
+	struct apple_pcie_port *port;
+	u32 link_stat, idx;
+	int ret, i;
+	char name[16];
+
+	port = devm_kzalloc(pcie->dev, sizeof(*port), GFP_KERNEL);
+	if (!port)
+		return -ENOMEM;
+
+	ret = of_property_read_u32_index(np, "reg", 0, &idx);
+	if (ret)
+		return ret;
+
+	/* Use the first reg entry to work out the port index */
+	port->idx = idx >> 11;
+	port->pcie = pcie;
+	port->np = np;
+
+	snprintf(name, sizeof(name), "port%d", port->idx);
+	port->base = devm_platform_ioremap_resource_byname(platform, name);
+	if (IS_ERR(port->base))
+		port->base = devm_platform_ioremap_resource(platform, port->idx + 2);
+	if (IS_ERR(port->base)) {
+		return PTR_ERR(port->base);
+	}
+
+	snprintf(name, sizeof(name), "phy%d", port->idx);
+	port->phy = devm_platform_ioremap_resource_byname(platform, name);
+	if (IS_ERR(port->phy))
+		port->phy = pcie->base + CORE_PHY_DEFAULT_BASE(port->idx);
+
+	/* link might be already brought up by u-boot, skip setup then */
+	link_stat = readl_relaxed(port->base + PORT_LINKSTS);
+	if (!(link_stat & PORT_LINKSTS_UP)) {
+		ret = apple_pcie_setup_link(pcie, port, np);
+		if (ret)
+			return ret;
+	}
+
 	ret = apple_pcie_port_setup_irq(port);
 	if (ret)
 		return ret;
@@ -714,6 +732,10 @@ static int apple_pcie_setup_port(struct apple_pcie *pcie,
 	ret = apple_pcie_port_register_irqs(port);
 	WARN_ON(ret);
 
+	if (link_stat & PORT_LINKSTS_UP)
+		return 0;
+
+	/* start link training */
 	writel_relaxed(PORT_LTSSMCTL_START, port->base + PORT_LTSSMCTL);
 
 	if (!wait_for_completion_timeout(&pcie->event, HZ / 10))