Skip to content

Bug in axis_sim_stim.vhd file #3

@Vic0428

Description

@Vic0428

Hi all,

Thanks for your great work and I really love NetFPGA project!

I found there maybe one bug in the axis_sim_stim.vhd file. It handles @(N) as same as +(N) and doesn't provide the semantic of wait until some absolute time.

            -- operator @(N): wait until absolute time N ns
            	elsif c = '@' then          -- wait until absolute time (ns)              
		    read_char( l, c );      -- discard operator
         	    parse_int( l, i );
            	    quiescent;
		    wait for ( i * 1 ns);
                    wait_cycle;

            -- operator +(N): wait for N ns
            	elsif c = '+' then          -- wait for relative time (ns)
               	    read_char( l, c );      -- discard operator
                    parse_int( l, i );
                    quiescent;
		    wait for ( i * 1 ns);                
                    wait_cycle;

Have a nice day!

Thanks,
Vic

Metadata

Metadata

Assignees

No one assigned

    Labels

    No labels
    No labels

    Type

    No type
    No fields configured for issues without a type.

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions