drv_timer.c

/*
 * Copyright (c) 2006-2025, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2023-09-04     Rbb666       first version
 */

#include "board.h"
#include "drv_timer.h"

//#define DRV_DEBUG
#define LOG_TAG             "drv.timer"
#include <rtdbg.h>

#ifdef RT_USING_CLOCK_TIME

#define GPT_GTWP_RESET_VALUE (0xA500U)

#ifdef SOC_SERIES_R9A07G0
#define TIMER_FSP_PRIV_CLOCK FSP_PRIV_CLOCK_PCLKGPTL
#else
#define TIMER_FSP_PRIV_CLOCK FSP_PRIV_CLOCK_PCLKD
#endif

static struct ra_clock_timer ra_clock_timer_obj[BSP_TIMERS_NUM] =
{
#ifdef BSP_USING_TIM0
    [BSP_TIMER0_INDEX] = TIMER_DRV_INITIALIZER(0),
#endif
#ifdef BSP_USING_TIM1
    [BSP_TIMER1_INDEX] = TIMER_DRV_INITIALIZER(1),
#endif
};

const rt_uint32_t PLCKD_FREQ_PRESCALER[PLCKD_PRESCALER_MAX_SELECT] =
{
#if defined(SOC_SERIES_R7FA6M3)
    PLCKD_PRESCALER_120M,
    PLCKD_PRESCALER_60M,
    PLCKD_PRESCALER_30M,
    PLCKD_PRESCALER_15M,
    PLCKD_PRESCALER_7_5M,
    PLCKD_PRESCALER_3_75M,
    PLCKD_PRESCALER_1_875M,
#elif defined(SOC_SERIES_R9A07G0)
    PLCKD_PRESCALER_400M,
    PLCKD_PRESCALER_200M,
    PLCKD_PRESCALER_100M,
    PLCKD_PRESCALER_50M,
    PLCKD_PRESCALER_25M,
    PLCKD_PRESCALER_12_5M,
    PLCKD_PRESCALER_6_25M,
    PLCKD_PRESCALER_3_125M,
    PLCKD_PRESCALER_1_5625M
#elif defined(SOC_SERIES_R7KA8P1)
    PLCKD_PRESCALER_250M,
    PLCKD_PRESCALER_200M,
    PLCKD_PRESCALER_100M,
    PLCKD_PRESCALER_50M,
    PLCKD_PRESCALER_25M,
    PLCKD_PRESCALER_12_5M,
    PLCKD_PRESCALER_6_25M,
    PLCKD_PRESCALER_3_125M,
    PLCKD_PRESCALER_1_5625M
#endif
};

static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state)
{
    RT_ASSERT(timer != RT_NULL);

    struct ra_clock_timer *tim;
    tim = (struct ra_clock_timer *)timer->parent.user_data;

    if (state)
    {
        fsp_err_t fsp_err = FSP_SUCCESS;

        fsp_err = R_GPT_Open(tim->g_ctrl, tim->g_cfg);

        if (fsp_err != FSP_SUCCESS)
        {
            LOG_E("%s init fail", tim->name);
        }
    }
}

static rt_err_t timer_start(rt_clock_timer_t *timer, rt_uint32_t pr, rt_clock_timer_mode_t opmode)
{
    RT_ASSERT(timer != RT_NULL);
    RT_ASSERT(opmode != RT_NULL);

    struct ra_clock_timer *tim;
    tim = (struct ra_clock_timer *)timer->parent.user_data;
    fsp_err_t err = FSP_SUCCESS;

    /* set timer count */
    R_GPT_CounterSet(tim->g_ctrl, 0);
    /* set timer period register */
    err = R_GPT_PeriodSet(tim->g_ctrl, pr);

    if (err != FSP_SUCCESS)
    {
        return -RT_ERROR;
    }

    /* set timer to one cycle mode */
    err = R_GPT_Start(tim->g_ctrl);

    return (err == FSP_SUCCESS) ? RT_EOK : -RT_ERROR;
}

static void timer_stop(rt_clock_timer_t *timer)
{
    struct ra_clock_timer *tim = RT_NULL;

    RT_ASSERT(timer != RT_NULL);
    tim = (struct ra_clock_timer *)timer->parent.user_data;

    /* stop timer */
    R_GPT_Stop(tim->g_ctrl);

    /* set timer count */
    R_GPT_CounterSet(tim->g_ctrl, 0);
}

static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer)
{
    struct ra_clock_timer *tim = RT_NULL;

    RT_ASSERT(timer != RT_NULL);

    tim = (struct ra_clock_timer *)timer->parent.user_data;

#if defined(SOC_SERIES_R7KA8P1)
    timer_info_t info;
    if (R_GPT_InfoGet(tim->g_ctrl, &info) != FSP_SUCCESS)
        return -RT_ERROR;

    return info.period_counts;
#else
    timer_status_t status;
    if (R_GPT_StatusGet(tim->g_ctrl, &status) != FSP_SUCCESS)
        return -RT_ERROR;

    return status.counter;
#endif
}

static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg)
{
    rt_err_t result = RT_EOK;
    struct ra_clock_timer *tim = RT_NULL;

    RT_ASSERT(timer != RT_NULL);
    RT_ASSERT(arg != RT_NULL);

    tim = (struct ra_clock_timer *)timer->parent.user_data;

    switch (cmd)
    {
    case CLOCK_TIMER_CTRL_FREQ_SET:
    {
        rt_uint32_t req_freq = *((rt_uint32_t *)arg);
        rt_uint32_t source_div = 0;
        rt_uint32_t actual_freq = 0;
        rt_uint32_t src_clk_hz = R_FSP_SystemClockHzGet(TIMER_FSP_PRIV_CLOCK);

#if (2U == BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE)
        for (rt_uint32_t div = 0; div <= 10U; div++)
#else
        for (rt_uint32_t div = 0; div <= 10U; div += 2U)
#endif
        {
#if (2U == BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE) && (0U == BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID)
            if ((7U == div) || (9U == div))
            {
                continue;
            }
#endif
            rt_uint32_t cand = src_clk_hz >> div;
            if (req_freq <= cand)
            {
                source_div = div;
                actual_freq = cand;
            }
        }

        if (0U == actual_freq)
        {
            /* Keep behavior bounded even with an unexpected input. */
            source_div = 10U;
            actual_freq = src_clk_hz >> source_div;
        }

        /* GPT TPCS can only be updated when counter is stopped and GTWP is unlocked. */
        R_GPT_Stop(tim->g_ctrl);
        uint32_t wp = tim->g_ctrl->p_reg->GTWP;
        tim->g_ctrl->p_reg->GTWP = GPT_GTWP_RESET_VALUE;
        (void) tim->g_ctrl->p_reg->GTWP;
        tim->g_ctrl->p_reg->GTCR_b.TPCS = (source_div >> BSP_FEATURE_GPT_TPCS_SHIFT);
        tim->g_ctrl->p_reg->GTWP = (wp | GPT_GTWP_RESET_VALUE);

        /* Return real hardware frequency to clock_timer core to keep conversion consistent. */
        *((rt_uint32_t *)arg) = actual_freq;
    }
    break;
    default:
    {
        result = -RT_ENOSYS;
    }
    break;
    }

    return result;
}

static void timer_one_shot_check(void)
{
    IRQn_Type irq = R_FSP_CurrentIrqGet();

    /* Recover ISR context saved in open. */
    gpt_instance_ctrl_t *p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);

    /* If one-shot mode is selected, stop the timer since period has expired. */
    if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
    {
        p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;

        /* Clear the GPT counter and the overflow flag after the one shot pulse has being generated */
        p_instance_ctrl->p_reg->GTCNT = 0;
        p_instance_ctrl->p_reg->GTCCR[0U] = 0;
        p_instance_ctrl->p_reg->GTCCR[1U] = 0;

        /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */
        R_BSP_IrqClearPending(irq);
    }
}

#ifdef BSP_USING_TIM0
void timer0_callback(timer_callback_args_t *p_args)
{
    /* enter interrupt */
    rt_interrupt_enter();

    if (TIMER_EVENT_CYCLE_END == p_args->event)
    {
        rt_clock_timer_isr(&ra_clock_timer_obj[BSP_TIMER0_INDEX].tmr_device);

        timer_one_shot_check();
    }

    /* leave interrupt */
    rt_interrupt_leave();
}
#endif

#ifdef BSP_USING_TIM1
void timer1_callback(timer_callback_args_t *p_args)
{
    /* enter interrupt */
    rt_interrupt_enter();

    if (TIMER_EVENT_CYCLE_END == p_args->event)
    {
        rt_clock_timer_isr(&ra_clock_timer_obj[BSP_TIMER1_INDEX].tmr_device);

        timer_one_shot_check();
    }

    /* leave interrupt */
    rt_interrupt_leave();
}
#endif

static const struct rt_clock_timer_ops _ops =
{
    .init = timer_init,
    .start = timer_start,
    .stop = timer_stop,
    .count_get = timer_counter_get,
    .control = timer_ctrl,
};

static const struct rt_clock_timer_info _info = TMR_DEV_INFO_CONFIG;

static int rt_hw_clock_timer_init(void)
{
    int result = RT_EOK;

    for (int i = 0; i < sizeof(ra_clock_timer_obj) / sizeof(ra_clock_timer_obj[0]); i++)
    {
        ra_clock_timer_obj[i].tmr_device.info = &_info;
        ra_clock_timer_obj[i].tmr_device.ops  = &_ops;
        if (rt_clock_timer_register(&ra_clock_timer_obj[i].tmr_device, ra_clock_timer_obj[i].name, &ra_clock_timer_obj[i]) == RT_EOK)
        {
            LOG_D("%s register success", ra_clock_timer_obj[i].name);
        }
        else
        {
            LOG_E("%s register failed", ra_clock_timer_obj[i].name);
            result = -RT_ERROR;
        }
    }

    return result;
}
INIT_BOARD_EXPORT(rt_hw_clock_timer_init);

/* This is a clock_timer example.
 * Use timer1 by default to avoid conflicting with the clock_time default event timer (timer0). */
#ifdef BSP_USING_TIM1
#define CLOCK_TIMER_DEV_NAME "timer1" /* device name */
#else
#define CLOCK_TIMER_DEV_NAME "timer0" /* fallback */
#endif

static rt_tick_t s_last_cb_tick = 0;

static void clock_timer_sample_prepare(rt_device_t hw_dev)
{
    struct ra_clock_timer *tim = (struct ra_clock_timer *)hw_dev->user_data;

    if (tim && tim->g_ctrl && tim->g_cfg)
    {
        R_GPT_Stop(tim->g_ctrl);
        R_GPT_CounterSet(tim->g_ctrl, 0);
        if (tim->g_cfg->cycle_end_irq >= 0)
        {
            R_BSP_IrqClearPending(tim->g_cfg->cycle_end_irq);
        }
    }
}

static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
{
    rt_tick_t now_tick = rt_tick_get();

    rt_kprintf("this is clock_timer timeout callback fucntion!\n");
    if (s_last_cb_tick)
    {
        rt_tick_t dt_tick = now_tick - s_last_cb_tick;
        rt_uint32_t dt_ms = (rt_uint32_t)(((rt_uint64_t)dt_tick * 1000ULL) / RT_TICK_PER_SECOND);
        rt_kprintf("tick is :%d ! dt_tick=%d, dt_ms=%d\n",
                   (int)now_tick,
                   (int)dt_tick,
                   (int)dt_ms);
    }
    else
    {
        rt_kprintf("tick is :%d ! dt_tick=0, dt_ms=0 (first)\n", (int)now_tick);
    }
    s_last_cb_tick = now_tick;

    return RT_EOK;
}

int clock_timer_sample(void)
{
    rt_err_t ret = RT_EOK;
    rt_clock_timerval_t timeout_s;
    rt_device_t hw_dev = RT_NULL;
    rt_clock_timer_mode_t mode;
    rt_uint32_t freq = 1875000; /* 1.875MHz */

    hw_dev = rt_device_find(CLOCK_TIMER_DEV_NAME);
    if (hw_dev == RT_NULL)
    {
        rt_kprintf("clock_timer sample run failed! can't find %s device!\n", CLOCK_TIMER_DEV_NAME);
        return -RT_ERROR;
    }
    rt_kprintf("clock_timer sample using %s\n", CLOCK_TIMER_DEV_NAME);

    ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
    if (ret != RT_EOK)
    {
        rt_kprintf("open %s device failed!\n", CLOCK_TIMER_DEV_NAME);
        return ret;
    }

    /* Stop old run and clear pending flag before a new period is configured. */
    rt_device_control(hw_dev, CLOCK_TIMER_CTRL_STOP, RT_NULL);
    clock_timer_sample_prepare(hw_dev);
    s_last_cb_tick = 0;

    rt_device_set_rx_indicate(hw_dev, timeout_cb);

    rt_device_control(hw_dev, CLOCK_TIMER_CTRL_FREQ_SET, &freq);

    mode = CLOCK_TIMER_MODE_PERIOD;
    ret = rt_device_control(hw_dev, CLOCK_TIMER_CTRL_MODE_SET, &mode);
    if (ret != RT_EOK)
    {
        rt_kprintf("set mode failed! ret is :%d\n", ret);
        return ret;
    }

    /* Example Set the timeout period of the timer */
    timeout_s.sec = 1;  /* secend */
    timeout_s.usec = 0; /* microsecend */
    if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
    {
        rt_kprintf("set timeout value failed\n");
        return -RT_ERROR;
    }

    /* read clock_timer value */
    rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
    rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);

    return ret;
}
MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample);

#endif /* BSP_USING_CLOCK_TIMER */