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goodnorning
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fix[libcpu][risc-v]:
 - Implement _noncache() and _cache() function features; - Correct rt_hw_mmu_setup function for NORMAL_NOCACHE_MEM type property configuration; - Update C908/C906 PTE macro definition configuration;
1 parent 0dfc5f3 commit 33f8aff

4 files changed

Lines changed: 94 additions & 18 deletions

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‎libcpu/risc-v/common64/mmu.c‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -740,12 +740,18 @@ void *rt_hw_mmu_v2p(struct rt_aspace *aspace, void *vaddr)
740740

741741
static int _noncache(rt_ubase_t *pte)
742742
{
743-
return 0;
743+
*pte &= ~PTE_PBMT_MASK;
744+
*pte |= PTE_PBMT_NC;
745+
rt_hw_cpu_dcache_clean(pte, sizeof(*pte));
746+
return RT_EOK;
744747
}
745748

746749
static int _cache(rt_ubase_t *pte)
747750
{
748-
return 0;
751+
*pte &= ~PTE_PBMT_MASK;
752+
*pte |= PTE_PBMT_PMA;
753+
rt_hw_cpu_dcache_clean(pte, sizeof(*pte));
754+
return RT_EOK;
749755
}
750756

751757
static int (*control_handler[MMU_CNTL_DUMMY_END])(rt_ubase_t *pte)=
@@ -829,7 +835,7 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
829835
attr = MMU_MAP_K_RWCB;
830836
break;
831837
case NORMAL_NOCACHE_MEM:
832-
attr = MMU_MAP_K_RWCB;
838+
attr = MMU_MAP_K_RW;
833839
break;
834840
case DEVICE_MEM:
835841
attr = MMU_MAP_K_DEVICE;

‎libcpu/risc-v/t-head/c906/riscv_mmu.h‎

Lines changed: 65 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,12 +19,31 @@
1919

2020
#undef PAGE_SIZE
2121

22-
/* C-SKY extend */
22+
#if !CONFIG_XUANTIE_SVPBMT
23+
/*
24+
* RISC-V Standard Svpbmt Extension (Bit 61-62)
25+
* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
26+
* 01: NC (Non-cacheable, Weakly-ordered)
27+
* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
28+
* 11: Reserved
29+
*/
30+
#define PTE_PBMT_PMA (0UL << 61)
31+
#define PTE_PBMT_NC (1UL << 61)
32+
#define PTE_PBMT_IO (2UL << 61)
33+
#define PTE_PBMT_MASK (3UL << 61)
34+
#else
35+
/* XuanTie Extension (Bit 59-63) */
2336
#define PTE_SEC (1UL << 59) /* Security */
2437
#define PTE_SHARE (1UL << 60) /* Shareable */
2538
#define PTE_BUF (1UL << 61) /* Bufferable */
2639
#define PTE_CACHE (1UL << 62) /* Cacheable */
2740
#define PTE_SO (1UL << 63) /* Strong Order */
41+
/* Compatible with Standard Svpbmt */
42+
#define PTE_PBMT_PMA (PTE_CACHE | PTE_BUF | PTE_SHARE)
43+
#define PTE_PBMT_NC (PTE_BUF | PTE_SHARE)
44+
#define PTE_PBMT_IO (PTE_SO | PTE_SHARE)
45+
#define PTE_PBMT_MASK (PTE_PBMT_PMA | PTE_PBMT_IO | PTE_SEC)
46+
#endif
2847

2948
#define PAGE_OFFSET_SHIFT 0
3049
#define PAGE_OFFSET_BIT 12
@@ -65,11 +84,20 @@
6584
#define PAGE_ATTR_CB (PTE_BUF | PTE_CACHE)
6685
#define PAGE_ATTR_DEV (PTE_SO)
6786

87+
#if !CONFIG_XUANTIE_SVPBMT
88+
/*
89+
* Default Leaf Attribute:
90+
* RWX + User + Valid + Global + Accessed + Dirty + PMA(Cacheable)
91+
*/
92+
#define PAGE_DEFAULT_ATTR_LEAF \
93+
(PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_PBMT_PMA | PTE_A | PTE_D)
94+
#else
6895
#define PAGE_DEFAULT_ATTR_LEAF \
6996
(PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_U | \
7097
PAGE_ATTR_RWX | PTE_V)
71-
#define PAGE_DEFAULT_ATTR_NEXT \
72-
(PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_V)
98+
#endif
99+
100+
#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G)
73101

74102
#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)
75103

@@ -89,6 +117,38 @@
89117
#define ARCH_VADDR_WIDTH 39
90118
#define SATP_MODE SATP_MODE_SV39
91119

120+
#if !CONFIG_XUANTIE_SVPBMT
121+
/*
122+
* Kernel Mappings
123+
*/
124+
/* Device: IO Mode (Strongly Ordered) */
125+
#define MMU_MAP_K_DEVICE (PTE_PBMT_IO | PTE_A | PTE_D | PTE_G | PTE_W | PTE_R | PTE_V)
126+
127+
/* RW: Non-Cacheable (NC Mode) */
128+
#define MMU_MAP_K_RW (PTE_PBMT_NC | PTE_A | PTE_D | PTE_G | PAGE_ATTR_RWX | PTE_V)
129+
130+
/* RWCB: Cacheable (PMA Mode) - Normal RAM */
131+
#define MMU_MAP_K_RWCB (PTE_PBMT_PMA | PTE_A | PTE_D | PTE_G | PAGE_ATTR_RWX | PTE_V)
132+
133+
/*
134+
* User Mappings
135+
*/
136+
/* User RW: Non-Cacheable */
137+
#define MMU_MAP_U_RW (PTE_PBMT_NC | PTE_U | PTE_A | PTE_D | PAGE_ATTR_RWX | PTE_V)
138+
139+
/* User RWCB: Cacheable */
140+
#define MMU_MAP_U_RWCB (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_RWX | PTE_V)
141+
142+
/* User ROCB: Cacheable */
143+
#define MMU_MAP_U_ROCB (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_READONLY | PTE_V)
144+
145+
/* User RWCB: Cacheable */
146+
#define MMU_MAP_U_RWCB_XN (PTE_PBMT_PMA | PTE_U | PTE_A | PTE_D | PAGE_ATTR_XN | PTE_V)
147+
148+
/* Early Mapping: Cacheable */
149+
#define MMU_MAP_EARLY \
150+
PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_PBMT_PMA)
151+
#else
92152
#define MMU_MAP_K_DEVICE PTE_WRAP(PAGE_ATTR_DEV | PTE_G | PAGE_ATTR_XN | PTE_V)
93153
#define MMU_MAP_K_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_G | PAGE_ATTR_RWX | PTE_V)
94154
#define MMU_MAP_K_RW PTE_WRAP(PTE_G | PAGE_ATTR_RWX | PTE_V)
@@ -99,6 +159,8 @@
99159
#define MMU_MAP_U_RW PTE_WRAP(PTE_U | PAGE_ATTR_RWX | PTE_V)
100160
#define MMU_MAP_EARLY \
101161
PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_CACHE | PTE_SHARE | PTE_BUF)
162+
#endif
163+
102164
#define MMU_MAP_TRACE(attr) (attr)
103165

104166
#define PTE_XWR_MASK 0xe

‎libcpu/risc-v/t-head/c908/riscv_mmu.h‎

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -23,22 +23,27 @@
2323
#if !CONFIG_XUANTIE_SVPBMT
2424
/*
2525
* RISC-V Standard Svpbmt Extension (Bit 61-62)
26-
* 00: PMA (Normal Memory, Cacheable)
26+
* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
2727
* 01: NC (Non-cacheable, Weakly-ordered)
2828
* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
2929
* 11: Reserved
3030
*/
31-
#define PTE_PBMT_MASK (3UL << 61)
3231
#define PTE_PBMT_PMA (0UL << 61)
3332
#define PTE_PBMT_NC (1UL << 61)
3433
#define PTE_PBMT_IO (2UL << 61)
34+
#define PTE_PBMT_MASK (3UL << 61)
3535
#else
3636
/* XuanTie Extension (Bit 59-63) */
3737
#define PTE_SEC (1UL << 59) /* Security */
3838
#define PTE_SHARE (1UL << 60) /* Shareable */
3939
#define PTE_BUF (1UL << 61) /* Bufferable */
4040
#define PTE_CACHE (1UL << 62) /* Cacheable */
4141
#define PTE_SO (1UL << 63) /* Strong Order */
42+
/* Compatible with Standard Svpbmt */
43+
#define PTE_PBMT_PMA (PTE_CACHE | PTE_BUF | PTE_SHARE)
44+
#define PTE_PBMT_NC (PTE_BUF | PTE_SHARE)
45+
#define PTE_PBMT_IO (PTE_SO | PTE_SHARE)
46+
#define PTE_PBMT_MASK (PTE_PBMT_PMA | PTE_PBMT_IO | PTE_SEC)
4247
#endif
4348

4449
#define PAGE_OFFSET_SHIFT 0
@@ -82,22 +87,13 @@
8287
*/
8388
#define PAGE_DEFAULT_ATTR_LEAF \
8489
(PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_PBMT_PMA | PTE_A | PTE_D)
85-
86-
/*
87-
* Next Level Attribute:
88-
* Svpbmt spec requires PBMT bits to be 0 for non-leaf PTEs.
89-
*/
90-
#define PAGE_DEFAULT_ATTR_NEXT \
91-
(PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G | PTE_A | PTE_D)
9290
#else
9391
#define PAGE_DEFAULT_ATTR_LEAF \
9492
(PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | \
9593
PTE_CACHE | PTE_A | PTE_D)
96-
97-
#define PAGE_DEFAULT_ATTR_NEXT \
98-
(PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D)
9994
#endif
10095

96+
#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G)
10197
#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)
10298

10399
#define PTE_USED(pte) __MASKVALUE(pte, PTE_V)

‎libcpu/risc-v/virt64/riscv_mmu.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,18 @@
1818

1919
#undef PAGE_SIZE
2020

21+
/*
22+
* RISC-V Standard Svpbmt Extension (Bit 61-62)
23+
* 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
24+
* 01: NC (Non-cacheable, Weakly-ordered)
25+
* 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
26+
* 11: Reserved
27+
*/
28+
#define PTE_PBMT_PMA (0UL << 61)
29+
#define PTE_PBMT_NC (1UL << 61)
30+
#define PTE_PBMT_IO (2UL << 61)
31+
#define PTE_PBMT_MASK (3UL << 61)
32+
2133
#define PAGE_OFFSET_SHIFT 0
2234
#define PAGE_OFFSET_BIT 12
2335
#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)

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