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wdfk-progwdfk-prog
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feat:[STM32][I2C]:Distinguish STM32 I2C timing semantics by IP generation
1 parent 8be4b05 commit b361b40

5 files changed

Lines changed: 395 additions & 35 deletions

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‎bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ extern "C" {
2222
#define I2C1_BUS_CONFIG \
2323
{ \
2424
.Instance = I2C1, \
25+
.timing = 100000, \
2526
.timeout=0x1000, \
2627
.name = "hwi2c1", \
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.evirq_type = I2C1_EV_IRQn, \
@@ -57,6 +58,7 @@ extern "C" {
5758
#define I2C2_BUS_CONFIG \
5859
{ \
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.Instance = I2C2, \
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.timing = 100000, \
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.timeout=0x1000, \
6163
.name = "hwi2c2", \
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.evirq_type = I2C2_EV_IRQn, \
@@ -92,6 +94,7 @@ extern "C" {
9294
#define I2C3_BUS_CONFIG \
9395
{ \
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.Instance = I2C3, \
97+
.timing = 100000, \
9598
.timeout=0x1000, \
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.name = "hwi2c3", \
97100
.evirq_type = I2C3_EV_IRQn, \

‎bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ extern "C" {
2323
#define I2C1_BUS_CONFIG \
2424
{ \
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.Instance = I2C1, \
26-
.timing=0x10707DBC, \
26+
.timing = 100000, \
2727
.timeout=0x1000, \
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.name = "hwi2c1", \
2929
.evirq_type = I2C1_EV_IRQn, \
@@ -81,7 +81,7 @@ extern "C" {
8181
#define I2C2_BUS_CONFIG \
8282
{ \
8383
.Instance = I2C2, \
84-
.timing=0x10707DBC, \
84+
.timing = 100000, \
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.timeout=0x1000, \
8686
.name = "hwi2c2", \
8787
.evirq_type = I2C2_EV_IRQn, \
@@ -139,7 +139,7 @@ extern "C" {
139139
#define I2C3_BUS_CONFIG \
140140
{ \
141141
.Instance = I2C3, \
142-
.timing=0x10707DBC, \
142+
.timing = 100000, \
143143
.timeout=0x1000, \
144144
.name = "hwi2c3", \
145145
.evirq_type = I2C3_EV_IRQn, \
@@ -197,7 +197,7 @@ extern "C" {
197197
#define I2C4_BUS_CONFIG \
198198
{ \
199199
.Instance = I2C4, \
200-
.timing = 0x10707DBC, \
200+
.timing = 100000, \
201201
.timeout = 0x1000, \
202202
.name = "hwi2c4", \
203203
.evirq_type = I2C4_EV_IRQn, \

‎bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/i2c_hard_config.h‎

Lines changed: 258 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,258 @@
1+
/*
2+
* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
7+
* Date Author Notes
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* 2024-02-06 Dyyt587 first version
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* 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG
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* 2024-06-23 wdfk-prog Add H7 hard I2C config
11+
*/
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#ifndef __I2C_HARD_CONFIG_H__
13+
#define __I2C_HARD_CONFIG_H__
14+
15+
#include <rtthread.h>
16+
17+
#ifdef __cplusplus
18+
extern "C" {
19+
#endif
20+
21+
#ifdef BSP_USING_HARD_I2C1
22+
#ifndef I2C1_BUS_CONFIG
23+
#define I2C1_BUS_CONFIG \
24+
{ \
25+
.Instance = I2C1, \
26+
.timing = 0x307075B1, \
27+
.timeout = 1000, \
28+
.name = "hwi2c1", \
29+
.evirq_type = I2C1_EV_IRQn, \
30+
.erirq_type = I2C1_ER_IRQn, \
31+
}
32+
#endif /* I2C1_BUS_CONFIG */
33+
#endif /* BSP_USING_HARD_I2C1 */
34+
35+
#ifdef BSP_I2C1_TX_USING_DMA
36+
#ifndef I2C1_TX_DMA_CONFIG
37+
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
38+
#define I2C1_TX_DMA_CONFIG \
39+
{ \
40+
.dma_rcc = I2C1_TX_DMA_RCC, \
41+
.Instance = I2C1_TX_DMA_INSTANCE, \
42+
.dma_irq = I2C1_TX_DMA_IRQ, \
43+
.channel = I2C1_TX_DMA_CHANNEL \
44+
}
45+
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
46+
#define I2C1_TX_DMA_CONFIG \
47+
{ \
48+
.dma_rcc = I2C1_TX_DMA_RCC, \
49+
.Instance = I2C1_TX_DMA_INSTANCE, \
50+
.dma_irq = I2C1_TX_DMA_IRQ, \
51+
.request = DMA_REQUEST_I2C1_TX \
52+
}
53+
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
54+
#endif /* I2C1_TX_DMA_CONFIG */
55+
#endif /* BSP_I2C1_TX_USING_DMA */
56+
57+
#ifdef BSP_I2C1_RX_USING_DMA
58+
#ifndef I2C1_RX_DMA_CONFIG
59+
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
60+
#define I2C1_RX_DMA_CONFIG \
61+
{ \
62+
.dma_rcc = I2C1_RX_DMA_RCC, \
63+
.Instance = I2C1_RX_DMA_INSTANCE, \
64+
.dma_irq = I2C1_RX_DMA_IRQ, \
65+
.channel = I2C1_RX_DMA_CHANNEL, \
66+
}
67+
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
68+
#define I2C1_RX_DMA_CONFIG \
69+
{ \
70+
.dma_rcc = I2C1_RX_DMA_RCC, \
71+
.Instance = I2C1_RX_DMA_INSTANCE, \
72+
.dma_irq = I2C1_RX_DMA_IRQ, \
73+
.request = DMA_REQUEST_I2C1_RX \
74+
}
75+
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
76+
#endif /* I2C1_RX_DMA_CONFIG */
77+
#endif /* BSP_I2C1_RX_USING_DMA */
78+
79+
#ifdef BSP_USING_HARD_I2C2
80+
#ifndef I2C2_BUS_CONFIG
81+
#define I2C2_BUS_CONFIG \
82+
{ \
83+
.Instance = I2C2, \
84+
.timing = 0x307075B1, \
85+
.timeout = 1000, \
86+
.name = "hwi2c2", \
87+
.evirq_type = I2C2_EV_IRQn, \
88+
.erirq_type = I2C2_ER_IRQn, \
89+
}
90+
#endif /* I2C2_BUS_CONFIG */
91+
#endif /* BSP_USING_HARD_I2C2 */
92+
93+
#ifdef BSP_I2C2_TX_USING_DMA
94+
#ifndef I2C2_TX_DMA_CONFIG
95+
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
96+
#define I2C2_TX_DMA_CONFIG \
97+
{ \
98+
.dma_rcc = I2C2_TX_DMA_RCC, \
99+
.Instance = I2C2_TX_DMA_INSTANCE, \
100+
.dma_irq = I2C2_TX_DMA_IRQ, \
101+
.channel = I2C2_TX_DMA_CHANNEL, \
102+
}
103+
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
104+
#define I2C2_TX_DMA_CONFIG \
105+
{ \
106+
.dma_rcc = I2C2_TX_DMA_RCC, \
107+
.Instance = I2C2_TX_DMA_INSTANCE, \
108+
.dma_irq = I2C2_TX_DMA_IRQ, \
109+
.request = DMA_REQUEST_I2C2_TX \
110+
}
111+
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
112+
#endif /* I2C2_TX_DMA_CONFIG */
113+
#endif /* BSP_I2C2_TX_USING_DMA */
114+
115+
#ifdef BSP_I2C2_RX_USING_DMA
116+
#ifndef I2C2_RX_DMA_CONFIG
117+
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
118+
#define I2C2_RX_DMA_CONFIG \
119+
{ \
120+
.dma_rcc = I2C2_RX_DMA_RCC, \
121+
.Instance = I2C2_RX_DMA_INSTANCE, \
122+
.dma_irq = I2C2_RX_DMA_IRQ, \
123+
.channel = I2C2_RX_DMA_CHANNEL, \
124+
}
125+
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
126+
#define I2C2_RX_DMA_CONFIG \
127+
{ \
128+
.dma_rcc = I2C2_RX_DMA_RCC, \
129+
.Instance = I2C2_RX_DMA_INSTANCE, \
130+
.dma_irq = I2C2_RX_DMA_IRQ, \
131+
.request = DMA_REQUEST_I2C2_RX \
132+
}
133+
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
134+
#endif /* I2C2_RX_DMA_CONFIG */
135+
#endif /* BSP_I2C2_RX_USING_DMA */
136+
137+
#ifdef BSP_USING_HARD_I2C3
138+
#ifndef I2C3_BUS_CONFIG
139+
#define I2C3_BUS_CONFIG \
140+
{ \
141+
.Instance = I2C3, \
142+
.timing = 0x307075B1, \
143+
.timeout = 1000, \
144+
.name = "hwi2c3", \
145+
.evirq_type = I2C3_EV_IRQn, \
146+
.erirq_type = I2C3_ER_IRQn, \
147+
}
148+
#endif /* I2C3_BUS_CONFIG */
149+
#endif /* BSP_USING_HARD_I2C3 */
150+
151+
#ifdef BSP_I2C3_TX_USING_DMA
152+
#ifndef I2C3_TX_DMA_CONFIG
153+
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
154+
#define I2C3_TX_DMA_CONFIG \
155+
{ \
156+
.dma_rcc = I2C3_TX_DMA_RCC, \
157+
.Instance = I2C3_TX_DMA_INSTANCE, \
158+
.dma_irq = I2C3_TX_DMA_IRQ, \
159+
.channel = I2C3_TX_DMA_CHANNEL, \
160+
}
161+
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
162+
#define I2C3_TX_DMA_CONFIG \
163+
{ \
164+
.dma_rcc = I2C3_TX_DMA_RCC, \
165+
.Instance = I2C3_TX_DMA_INSTANCE, \
166+
.dma_irq = I2C3_TX_DMA_IRQ, \
167+
.request = DMA_REQUEST_I2C3_TX \
168+
}
169+
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
170+
#endif /* I2C3_TX_DMA_CONFIG */
171+
#endif /* BSP_I2C3_TX_USING_DMA */
172+
173+
#ifdef BSP_I2C3_RX_USING_DMA
174+
#ifndef I2C3_RX_DMA_CONFIG
175+
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
176+
#define I2C3_RX_DMA_CONFIG \
177+
{ \
178+
.dma_rcc = I2C3_RX_DMA_RCC, \
179+
.Instance = I2C3_RX_DMA_INSTANCE, \
180+
.dma_irq = I2C3_RX_DMA_IRQ, \
181+
.channel = I2C3_RX_DMA_CHANNEL, \
182+
}
183+
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
184+
#define I2C3_RX_DMA_CONFIG \
185+
{ \
186+
.dma_rcc = I2C3_RX_DMA_RCC, \
187+
.Instance = I2C3_RX_DMA_INSTANCE, \
188+
.dma_irq = I2C3_RX_DMA_IRQ, \
189+
.request = DMA_REQUEST_I2C3_RX \
190+
}
191+
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
192+
#endif /* I2C3_RX_DMA_CONFIG */
193+
#endif /* BSP_I2C3_RX_USING_DMA */
194+
195+
#ifdef BSP_USING_HARD_I2C4
196+
#ifndef I2C4_BUS_CONFIG
197+
#define I2C4_BUS_CONFIG \
198+
{ \
199+
.Instance = I2C4, \
200+
.timing = 0x307075B1, \
201+
.timeout = 1000, \
202+
.name = "hwi2c4", \
203+
.evirq_type = I2C4_EV_IRQn, \
204+
.erirq_type = I2C4_ER_IRQn, \
205+
}
206+
#endif /* I2C4_BUS_CONFIG */
207+
#endif /* BSP_USING_HARD_I2C4 */
208+
209+
#ifdef BSP_I2C4_TX_USING_DMA
210+
#ifndef I2C4_TX_DMA_CONFIG
211+
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
212+
#define I2C4_TX_DMA_CONFIG \
213+
{ \
214+
.dma_rcc = I2C4_TX_DMA_RCC, \
215+
.Instance = I2C4_TX_DMA_INSTANCE, \
216+
.dma_irq = I2C4_TX_DMA_IRQ, \
217+
.channel = I2C4_TX_DMA_CHANNEL, \
218+
}
219+
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
220+
#define I2C4_TX_DMA_CONFIG \
221+
{ \
222+
.dma_rcc = I2C4_TX_DMA_RCC, \
223+
.Instance = I2C4_TX_DMA_INSTANCE, \
224+
.dma_irq = I2C4_TX_DMA_IRQ, \
225+
.request = DMA_REQUEST_I2C4_TX \
226+
}
227+
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
228+
#endif /* I2C4_TX_DMA_CONFIG */
229+
#endif /* BSP_I2C4_TX_USING_DMA */
230+
231+
#ifdef BSP_I2C4_RX_USING_DMA
232+
#ifndef I2C4_RX_DMA_CONFIG
233+
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
234+
#define I2C4_RX_DMA_CONFIG \
235+
{ \
236+
.dma_rcc = I2C4_RX_DMA_RCC, \
237+
.Instance = I2C4_RX_DMA_INSTANCE, \
238+
.dma_irq = I2C4_RX_DMA_IRQ, \
239+
.channel = I2C4_RX_DMA_CHANNEL, \
240+
}
241+
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
242+
#define I2C4_RX_DMA_CONFIG \
243+
{ \
244+
.dma_rcc = I2C4_RX_DMA_RCC, \
245+
.Instance = I2C4_RX_DMA_INSTANCE, \
246+
.dma_irq = I2C4_RX_DMA_IRQ, \
247+
.request = DMA_REQUEST_I2C4_RX \
248+
}
249+
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
250+
#endif /* I2C4_RX_DMA_CONFIG */
251+
#endif /* BSP_I2C4_RX_USING_DMA */
252+
253+
254+
#ifdef __cplusplus
255+
}
256+
#endif
257+
258+
#endif /*__I2C_CONFIG_H__ */

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