Fix OpSwitch target index logic in validator CFG analysis

The validator's OpSwitch operand parsing used index==1||index%2==0 which
selects indices {1,2,4,6,...} — grabbing literal case values at even
positions instead of block target IDs at odd positions. The correct
predicate is index%2==1 which selects {1,3,5,7,...} (default target at
index 1 plus case targets at indices 3,5,7,...).

This caused false "continue block not reachable from loop header" errors
when loops were inside switch case blocks, because the CFG was missing
edges from the switch to its case targets.

Author: LegNeato

rust/spirv-tools-core/src/validation/cfg_analysis.rs

@@ -69,12 +69,19 @@ fn get_branch_targets(terminator: &Instruction) -> Vec<Id> {
         }
         Op::Switch => {
             // Operands: selector, default target, then pairs of (literal, target)
+            // In rspirv's representation:
+            //   [0] = IdRef(selector)
+            //   [1] = IdRef(default_target)
+            //   [2] = LiteralBit32(case_val_0), [3] = IdRef(case_target_0)
+            //   [4] = LiteralBit32(case_val_1), [5] = IdRef(case_target_1)
+            //   ...
+            // So targets are at all ODD indices (1, 3, 5, 7, ...)
             for (index, op) in terminator.operands.iter().enumerate() {
                 if index == 0 {
                     continue; // skip selector
                 }
-                // Default target is at index 1, then case targets are at even indices (2, 4, 6, ...)
-                if index == 1 || index % 2 == 0 {
+                // Default target is at index 1, case targets at odd indices >= 3
+                if index % 2 == 1 {
                     if let Operand::IdRef(target) = op {
                         if let Some(id) = to_id(*target) {
                             if !targets.contains(&id) {

rust/spirv-tools-core/src/validation/mod.rs

@@ -1740,7 +1740,7 @@ fn is_block_operand(opcode: rspirv::spirv::Op, index: usize) -> bool {
     match opcode {
         rspirv::spirv::Op::Branch => index == 0,
         rspirv::spirv::Op::BranchConditional => index == 1 || index == 2,
-        rspirv::spirv::Op::Switch => index == 1 || (index > 1 && index % 2 == 0),
+        rspirv::spirv::Op::Switch => index % 2 == 1,
         rspirv::spirv::Op::LoopMerge => index <= 1,
         rspirv::spirv::Op::SelectionMerge => index == 0,
         rspirv::spirv::Op::Phi => index % 2 == 1,

rust/spirv-tools-core/src/validation/rules/cfg.rs

@@ -647,11 +647,12 @@ impl ValidationRule for BranchTargetRule {
                                 .iter()
                                 .enumerate()
                                 .filter_map(|(idx, op)| {
-                                    // Skip selector (idx 0), include default (idx 1) and case targets (even indices)
+                                    // Skip selector (idx 0); default target is at idx 1,
+                                    // case targets at odd indices >= 3 (literal/target pairs)
                                     if idx == 0 {
                                         return None;
                                     }
-                                    if idx == 1 || idx % 2 == 0 {
+                                    if idx % 2 == 1 {
                                         if let Operand::IdRef(raw) = op {
                                             return Some(to_id(*raw));
                                         }

rust/spirv-tools-core/src/validation/rules/types/general.rs

@@ -183,7 +183,7 @@ fn is_block_operand(opcode: Op, index: usize) -> bool {
     match opcode {
         Op::Branch => index == 0,
         Op::BranchConditional => index == 1 || index == 2,
-        Op::Switch => index == 1 || (index > 1 && index % 2 == 0),
+        Op::Switch => index % 2 == 1,
         Op::LoopMerge => index <= 1,
         Op::SelectionMerge => index == 0,
         Op::Phi => index % 2 == 1,