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Benjamin Gaignardmchehab
Benjamin Gaignard
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mchehab
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media: verisilicon: Enable AV1 decoder on rk3588
Add rk3588 AV1 decoder to Hantro variant. The hardware support image from 64x64 up to 7680x4320 by steps of 16 pixels. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
1 parent d8ebe59 commit 003afda

3 files changed

Lines changed: 137 additions & 0 deletions

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‎drivers/media/platform/verisilicon/hantro_drv.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -713,6 +713,7 @@ static const struct of_device_id of_hantro_match[] = {
713713
{ .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
714714
{ .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
715715
{ .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
716+
{ .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, },
716717
#endif
717718
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
718719
{ .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, },

‎drivers/media/platform/verisilicon/hantro_hw.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -403,11 +403,13 @@ extern const struct hantro_variant rk3328_vpu_variant;
403403
extern const struct hantro_variant rk3399_vpu_variant;
404404
extern const struct hantro_variant rk3568_vepu_variant;
405405
extern const struct hantro_variant rk3568_vpu_variant;
406+
extern const struct hantro_variant rk3588_vpu981_variant;
406407
extern const struct hantro_variant sama5d4_vdec_variant;
407408
extern const struct hantro_variant sunxi_vpu_variant;
408409

409410
extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
410411
extern const struct hantro_postproc_ops hantro_g2_postproc_ops;
412+
extern const struct hantro_postproc_ops rockchip_vpu981_postproc_ops;
411413

412414
extern const u32 hantro_vp8_dec_mc_filter[8][6];
413415

‎drivers/media/platform/verisilicon/rockchip_vpu_hw.c‎

Lines changed: 134 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,13 @@
1313
#include "hantro_g1_regs.h"
1414
#include "hantro_h1_regs.h"
1515
#include "rockchip_vpu2_regs.h"
16+
#include "rockchip_vpu981_regs.h"
1617

1718
#define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
1819
#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
20+
#define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000)
21+
22+
#define ROCKCHIP_VPU981_MIN_SIZE 64
1923

2024
/*
2125
* Supported formats.
@@ -74,6 +78,37 @@ static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
7478
},
7579
};
7680

81+
static const struct hantro_fmt rockchip_vpu981_postproc_fmts[] = {
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{
83+
.fourcc = V4L2_PIX_FMT_NV12,
84+
.codec_mode = HANTRO_MODE_NONE,
85+
.match_depth = true,
86+
.postprocessed = true,
87+
.frmsize = {
88+
.min_width = ROCKCHIP_VPU981_MIN_SIZE,
89+
.max_width = FMT_UHD_WIDTH,
90+
.step_width = MB_DIM,
91+
.min_height = ROCKCHIP_VPU981_MIN_SIZE,
92+
.max_height = FMT_UHD_HEIGHT,
93+
.step_height = MB_DIM,
94+
},
95+
},
96+
{
97+
.fourcc = V4L2_PIX_FMT_P010,
98+
.codec_mode = HANTRO_MODE_NONE,
99+
.match_depth = true,
100+
.postprocessed = true,
101+
.frmsize = {
102+
.min_width = ROCKCHIP_VPU981_MIN_SIZE,
103+
.max_width = FMT_UHD_WIDTH,
104+
.step_width = MB_DIM,
105+
.min_height = ROCKCHIP_VPU981_MIN_SIZE,
106+
.max_height = FMT_UHD_HEIGHT,
107+
.step_height = MB_DIM,
108+
},
109+
},
110+
};
111+
77112
static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {
78113
{
79114
.fourcc = V4L2_PIX_FMT_NV12,
@@ -277,6 +312,48 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
277312
},
278313
};
279314

315+
static const struct hantro_fmt rockchip_vpu981_dec_fmts[] = {
316+
{
317+
.fourcc = V4L2_PIX_FMT_NV12_4L4,
318+
.codec_mode = HANTRO_MODE_NONE,
319+
.match_depth = true,
320+
.frmsize = {
321+
.min_width = ROCKCHIP_VPU981_MIN_SIZE,
322+
.max_width = FMT_UHD_WIDTH,
323+
.step_width = MB_DIM,
324+
.min_height = ROCKCHIP_VPU981_MIN_SIZE,
325+
.max_height = FMT_UHD_HEIGHT,
326+
.step_height = MB_DIM,
327+
},
328+
},
329+
{
330+
.fourcc = V4L2_PIX_FMT_NV15_4L4,
331+
.codec_mode = HANTRO_MODE_NONE,
332+
.match_depth = true,
333+
.frmsize = {
334+
.min_width = ROCKCHIP_VPU981_MIN_SIZE,
335+
.max_width = FMT_UHD_WIDTH,
336+
.step_width = MB_DIM,
337+
.min_height = ROCKCHIP_VPU981_MIN_SIZE,
338+
.max_height = FMT_UHD_HEIGHT,
339+
.step_height = MB_DIM,
340+
},
341+
},
342+
{
343+
.fourcc = V4L2_PIX_FMT_AV1_FRAME,
344+
.codec_mode = HANTRO_MODE_AV1_DEC,
345+
.max_depth = 2,
346+
.frmsize = {
347+
.min_width = ROCKCHIP_VPU981_MIN_SIZE,
348+
.max_width = FMT_UHD_WIDTH,
349+
.step_width = MB_DIM,
350+
.min_height = ROCKCHIP_VPU981_MIN_SIZE,
351+
.max_height = FMT_UHD_HEIGHT,
352+
.step_height = MB_DIM,
353+
},
354+
},
355+
};
356+
280357
static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
281358
{
282359
struct hantro_dev *vpu = dev_id;
@@ -331,6 +408,24 @@ static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id)
331408
return IRQ_HANDLED;
332409
}
333410

411+
static irqreturn_t rk3588_vpu981_irq(int irq, void *dev_id)
412+
{
413+
struct hantro_dev *vpu = dev_id;
414+
enum vb2_buffer_state state;
415+
u32 status;
416+
417+
status = vdpu_read(vpu, AV1_REG_INTERRUPT);
418+
state = (status & AV1_REG_INTERRUPT_DEC_RDY_INT) ?
419+
VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
420+
421+
vdpu_write(vpu, 0, AV1_REG_INTERRUPT);
422+
vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG);
423+
424+
hantro_irq_done(vpu, state);
425+
426+
return IRQ_HANDLED;
427+
}
428+
334429
static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
335430
{
336431
/* Bump ACLK to max. possible freq. to improve performance. */
@@ -346,6 +441,13 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
346441
return 0;
347442
}
348443

444+
static int rk3588_vpu981_hw_init(struct hantro_dev *vpu)
445+
{
446+
/* Bump ACLKs to max. possible freq. to improve performance. */
447+
clk_set_rate(vpu->clocks[0].clk, RK3588_ACLK_MAX_FREQ);
448+
return 0;
449+
}
450+
349451
static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
350452
{
351453
/* Bump ACLK to max. possible freq. to improve performance. */
@@ -498,6 +600,14 @@ static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = {
498600
},
499601
};
500602

603+
static const struct hantro_codec_ops rk3588_vpu981_codec_ops[] = {
604+
[HANTRO_MODE_AV1_DEC] = {
605+
.run = rockchip_vpu981_av1_dec_run,
606+
.init = rockchip_vpu981_av1_dec_init,
607+
.exit = rockchip_vpu981_av1_dec_exit,
608+
.done = rockchip_vpu981_av1_dec_done,
609+
},
610+
};
501611
/*
502612
* VPU variant.
503613
*/
@@ -529,10 +639,18 @@ static const char * const rk3066_vpu_clk_names[] = {
529639
"aclk_vepu", "hclk_vepu"
530640
};
531641

642+
static const struct hantro_irq rk3588_vpu981_irqs[] = {
643+
{ "vdpu", rk3588_vpu981_irq },
644+
};
645+
532646
static const char * const rockchip_vpu_clk_names[] = {
533647
"aclk", "hclk"
534648
};
535649

650+
static const char * const rk3588_vpu981_vpu_clk_names[] = {
651+
"aclk", "hclk", "aclk_vdpu_root", "hclk_vdpu_root"
652+
};
653+
536654
/* VDPU1/VEPU1 */
537655

538656
const struct hantro_variant rk3036_vpu_variant = {
@@ -678,3 +796,19 @@ const struct hantro_variant px30_vpu_variant = {
678796
.clk_names = rockchip_vpu_clk_names,
679797
.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
680798
};
799+
800+
const struct hantro_variant rk3588_vpu981_variant = {
801+
.dec_offset = 0x0,
802+
.dec_fmts = rockchip_vpu981_dec_fmts,
803+
.num_dec_fmts = ARRAY_SIZE(rockchip_vpu981_dec_fmts),
804+
.postproc_fmts = rockchip_vpu981_postproc_fmts,
805+
.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu981_postproc_fmts),
806+
.postproc_ops = &rockchip_vpu981_postproc_ops,
807+
.codec = HANTRO_AV1_DECODER,
808+
.codec_ops = rk3588_vpu981_codec_ops,
809+
.irqs = rk3588_vpu981_irqs,
810+
.num_irqs = ARRAY_SIZE(rk3588_vpu981_irqs),
811+
.init = rk3588_vpu981_hw_init,
812+
.clk_names = rk3588_vpu981_vpu_clk_names,
813+
.num_clocks = ARRAY_SIZE(rk3588_vpu981_vpu_clk_names)
814+
};

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