2929#define TH1520_HDMI_SW_MAIN_RST BIT(0)
3030#define TH1520_HDMI_SW_PRST BIT(1)
3131
32+ struct th1520_reset_map {
33+ u32 bit ;
34+ u32 reg ;
35+ };
36+
3237struct th1520_reset_priv {
3338 struct reset_controller_dev rcdev ;
3439 struct regmap * map ;
40+ const struct th1520_reset_map * resets ;
3541};
3642
37- struct th1520_reset_map {
38- u32 bit ;
39- u32 reg ;
43+ struct th1520_reset_data {
44+ const struct th1520_reset_map * resets ;
45+ size_t num ;
4046};
4147
4248static const struct th1520_reset_map th1520_resets [] = {
@@ -90,7 +96,7 @@ static int th1520_reset_assert(struct reset_controller_dev *rcdev,
9096 struct th1520_reset_priv * priv = to_th1520_reset (rcdev );
9197 const struct th1520_reset_map * reset ;
9298
93- reset = & th1520_resets [id ];
99+ reset = & priv -> resets [id ];
94100
95101 return regmap_update_bits (priv -> map , reset -> reg , reset -> bit , 0 );
96102}
@@ -101,7 +107,7 @@ static int th1520_reset_deassert(struct reset_controller_dev *rcdev,
101107 struct th1520_reset_priv * priv = to_th1520_reset (rcdev );
102108 const struct th1520_reset_map * reset ;
103109
104- reset = & th1520_resets [id ];
110+ reset = & priv -> resets [id ];
105111
106112 return regmap_update_bits (priv -> map , reset -> reg , reset -> bit ,
107113 reset -> bit );
@@ -120,11 +126,14 @@ static const struct regmap_config th1520_reset_regmap_config = {
120126
121127static int th1520_reset_probe (struct platform_device * pdev )
122128{
129+ const struct th1520_reset_data * data ;
123130 struct device * dev = & pdev -> dev ;
124131 struct th1520_reset_priv * priv ;
125132 void __iomem * base ;
126133 int ret ;
127134
135+ data = device_get_match_data (dev );
136+
128137 priv = devm_kzalloc (dev , sizeof (* priv ), GFP_KERNEL );
129138 if (!priv )
130139 return - ENOMEM ;
@@ -138,22 +147,31 @@ static int th1520_reset_probe(struct platform_device *pdev)
138147 if (IS_ERR (priv -> map ))
139148 return PTR_ERR (priv -> map );
140149
141- /* Initialize GPU resets to asserted state */
142- ret = regmap_update_bits (priv -> map , TH1520_GPU_RST_CFG ,
143- TH1520_GPU_RST_CFG_MASK , 0 );
144- if (ret )
145- return ret ;
150+ if (of_device_is_compatible (dev -> of_node , "thead,th1520-reset" )) {
151+ /* Initialize GPU resets to asserted state */
152+ ret = regmap_update_bits (priv -> map , TH1520_GPU_RST_CFG ,
153+ TH1520_GPU_RST_CFG_MASK , 0 );
154+ if (ret )
155+ return ret ;
156+ }
146157
147158 priv -> rcdev .owner = THIS_MODULE ;
148- priv -> rcdev .nr_resets = ARRAY_SIZE ( th1520_resets ) ;
159+ priv -> rcdev .nr_resets = data -> num ;
149160 priv -> rcdev .ops = & th1520_reset_ops ;
150161 priv -> rcdev .of_node = dev -> of_node ;
151162
163+ priv -> resets = data -> resets ;
164+
152165 return devm_reset_controller_register (dev , & priv -> rcdev );
153166}
154167
168+ static const struct th1520_reset_data th1520_reset_data = {
169+ .resets = th1520_resets ,
170+ .num = ARRAY_SIZE (th1520_resets ),
171+ };
172+
155173static const struct of_device_id th1520_reset_match [] = {
156- { .compatible = "thead,th1520-reset" },
174+ { .compatible = "thead,th1520-reset" , . data = & th1520_reset_data },
157175 { /* sentinel */ }
158176};
159177MODULE_DEVICE_TABLE (of , th1520_reset_match );
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