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Andre-ARMwens
Andre-ARM
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wens
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clk: sunxi-ng: a523: remaining mod clocks
Add the remaining mod clocks, driving various parts of the SoC: the "LEDC" LED controller, the "CSI" camera interface, the "ISP" image processor, the DSP clock, and the "fanout" clocks, which allow to put clock signals on external pins. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-12-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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‎drivers/clk/sunxi-ng/ccu-sun55i-a523.c‎

Lines changed: 185 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -862,6 +862,157 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_clk, "edp", edp_parents, 0xbb0,
862862
BIT(31), /* gate */
863863
CLK_SET_RATE_PARENT);
864864

865+
static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ir_tx_ledc_parents,
866+
0xbf0,
867+
0, 4, /* M */
868+
24, 1, /* mux */
869+
BIT(31), /* gate */
870+
0);
871+
872+
static const struct clk_hw *csi_top_parents[] = {
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&pll_periph0_300M_clk.hw,
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&pll_periph0_400M_clk.hw,
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&pll_periph0_480M_clk.common.hw,
876+
&pll_video3_4x_clk.common.hw,
877+
&pll_video3_3x_clk.hw,
878+
};
879+
static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents,
880+
0xc04,
881+
0, 5, /* M */
882+
24, 3, /* mux */
883+
BIT(31), /* gate */
884+
0);
885+
886+
static const struct clk_parent_data csi_mclk_parents[] = {
887+
{ .fw_name = "hosc" },
888+
{ .hw = &pll_video3_4x_clk.common.hw },
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{ .hw = &pll_video0_4x_clk.common.hw },
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{ .hw = &pll_video1_4x_clk.common.hw },
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{ .hw = &pll_video2_4x_clk.common.hw },
892+
};
893+
static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk0_clk, "csi-mclk0", csi_mclk_parents,
894+
0xc08,
895+
0, 5, /* M */
896+
8, 5, /* P */
897+
24, 3, /* mux */
898+
BIT(31), /* gate */
899+
0);
900+
901+
static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk1_clk, "csi-mclk1", csi_mclk_parents,
902+
0xc0c,
903+
0, 5, /* M */
904+
8, 5, /* P */
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24, 3, /* mux */
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BIT(31), /* gate */
907+
0);
908+
909+
static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk2_clk, "csi-mclk2", csi_mclk_parents,
910+
0xc10,
911+
0, 5, /* M */
912+
8, 5, /* P */
913+
24, 3, /* mux */
914+
BIT(31), /* gate */
915+
0);
916+
917+
static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk3_clk, "csi-mclk3", csi_mclk_parents,
918+
0xc14,
919+
0, 5, /* M */
920+
8, 5, /* P */
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24, 3, /* mux */
922+
BIT(31), /* gate */
923+
0);
924+
925+
static const struct clk_hw *isp_parents[] = {
926+
&pll_periph0_300M_clk.hw,
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&pll_periph0_400M_clk.hw,
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&pll_video2_4x_clk.common.hw,
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&pll_video3_4x_clk.common.hw,
930+
};
931+
static SUNXI_CCU_M_HW_WITH_MUX_GATE(isp_clk, "isp", isp_parents, 0xc20,
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0, 5, /* M */
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24, 3, /* mux */
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BIT(31), /* gate */
935+
0);
936+
937+
static const struct clk_parent_data dsp_parents[] = {
938+
{ .fw_name = "hosc" },
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{ .fw_name = "losc" },
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{ .fw_name = "iosc" },
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{ .hw = &pll_periph0_2x_clk.common.hw },
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{ .hw = &pll_periph0_480M_clk.common.hw, },
943+
};
944+
static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70,
945+
0, 5, /* M */
946+
24, 3, /* mux */
947+
BIT(31), /* gate */
948+
0);
949+
950+
static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
951+
0xf30, BIT(0), 0);
952+
static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
953+
0xf30, BIT(1), 2, 0);
954+
static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M",
955+
pll_periph0_480M_hws,
956+
0xf30, BIT(2), 30, 0);
957+
static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M",
958+
pll_periph0_2x_hws,
959+
0xf30, BIT(3), 48, 0);
960+
static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_50M_clk, "fanout-50M",
961+
pll_periph0_2x_hws,
962+
0xf30, BIT(4), 24, 0);
963+
964+
static const struct clk_parent_data fanout_27M_parents[] = {
965+
{ .hw = &pll_video0_4x_clk.common.hw },
966+
{ .hw = &pll_video1_4x_clk.common.hw },
967+
{ .hw = &pll_video2_4x_clk.common.hw },
968+
{ .hw = &pll_video3_4x_clk.common.hw },
969+
};
970+
static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M",
971+
fanout_27M_parents, 0xf34,
972+
0, 5, /* div0 */
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8, 5, /* div1 */
974+
24, 2, /* mux */
975+
BIT(31), /* gate */
976+
0);
977+
978+
static const struct clk_parent_data fanout_pclk_parents[] = {
979+
{ .hw = &apb0_clk.common.hw }
980+
};
981+
static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk",
982+
fanout_pclk_parents,
983+
0xf38,
984+
0, 5, /* div0 */
985+
5, 5, /* div1 */
986+
0, 0, /* mux */
987+
BIT(31), /* gate */
988+
0);
989+
990+
static const struct clk_parent_data fanout_parents[] = {
991+
{ .fw_name = "losc-fanout" },
992+
{ .hw = &fanout_12M_clk.common.hw, },
993+
{ .hw = &fanout_16M_clk.common.hw, },
994+
{ .hw = &fanout_24M_clk.common.hw, },
995+
{ .hw = &fanout_25M_clk.common.hw, },
996+
{ .hw = &fanout_27M_clk.common.hw, },
997+
{ .hw = &fanout_pclk_clk.common.hw, },
998+
{ .hw = &fanout_50M_clk.common.hw, },
999+
};
1000+
static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents,
1001+
0xf3c,
1002+
0, 3, /* mux */
1003+
BIT(21), /* gate */
1004+
0);
1005+
static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents,
1006+
0xf3c,
1007+
3, 3, /* mux */
1008+
BIT(22), /* gate */
1009+
0);
1010+
static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents,
1011+
0xf3c,
1012+
6, 3, /* mux */
1013+
BIT(23), /* gate */
1014+
0);
1015+
8651016
/*
8661017
* Contains all clocks that are controlled by a hardware register. They
8671018
* have a (sunxi) .common member, which needs to be initialised by the common
@@ -936,6 +1087,23 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
9361087
&tcon_tv0_clk.common,
9371088
&tcon_tv1_clk.common,
9381089
&edp_clk.common,
1090+
&ledc_clk.common,
1091+
&csi_top_clk.common,
1092+
&csi_mclk0_clk.common,
1093+
&csi_mclk1_clk.common,
1094+
&csi_mclk2_clk.common,
1095+
&csi_mclk3_clk.common,
1096+
&isp_clk.common,
1097+
&dsp_clk.common,
1098+
&fanout_24M_clk.common,
1099+
&fanout_12M_clk.common,
1100+
&fanout_16M_clk.common,
1101+
&fanout_25M_clk.common,
1102+
&fanout_27M_clk.common,
1103+
&fanout_pclk_clk.common,
1104+
&fanout0_clk.common,
1105+
&fanout1_clk.common,
1106+
&fanout2_clk.common,
9391107
};
9401108

9411109
static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
@@ -1031,6 +1199,23 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
10311199
[CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
10321200
[CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
10331201
[CLK_EDP] = &edp_clk.common.hw,
1202+
[CLK_LEDC] = &ledc_clk.common.hw,
1203+
[CLK_CSI_TOP] = &csi_top_clk.common.hw,
1204+
[CLK_CSI_MCLK0] = &csi_mclk0_clk.common.hw,
1205+
[CLK_CSI_MCLK1] = &csi_mclk1_clk.common.hw,
1206+
[CLK_CSI_MCLK2] = &csi_mclk2_clk.common.hw,
1207+
[CLK_CSI_MCLK3] = &csi_mclk3_clk.common.hw,
1208+
[CLK_ISP] = &isp_clk.common.hw,
1209+
[CLK_DSP] = &dsp_clk.common.hw,
1210+
[CLK_FANOUT_24M] = &fanout_24M_clk.common.hw,
1211+
[CLK_FANOUT_12M] = &fanout_12M_clk.common.hw,
1212+
[CLK_FANOUT_16M] = &fanout_16M_clk.common.hw,
1213+
[CLK_FANOUT_25M] = &fanout_25M_clk.common.hw,
1214+
[CLK_FANOUT_27M] = &fanout_27M_clk.common.hw,
1215+
[CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw,
1216+
[CLK_FANOUT0] = &fanout0_clk.common.hw,
1217+
[CLK_FANOUT1] = &fanout1_clk.common.hw,
1218+
[CLK_FANOUT2] = &fanout2_clk.common.hw,
10341219
},
10351220
};
10361221

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