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Michael Straussalexdeucher
Michael Strauss
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alexdeucher
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drm/amd/display: Update chip_cap defines and usage
[WHY] The defines have also been updated with prefix AMD_ and atomfirmware.h has been temporarily updated with both sets of defines to allow the transition. This update is being made to standardize workaround chip_cap flags, in order to support more workaround flags in the future. [HOW] Updated EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN define, the flag is now an enum masked by EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK. All checks for DP_FIXED_VS_EN are now performed by masking with EXT_CHIP_MASK and checking for an exact match rather than the previous bitwise AND check. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 3606115 commit 00d53a0

9 files changed

Lines changed: 21 additions & 20 deletions

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‎drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3088,11 +3088,12 @@ static enum bp_result construct_integrated_info(
30883088
info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id,
30893089
info->ext_disp_conn_info.path[i].caps
30903090
);
3091-
if (info->ext_disp_conn_info.path[i].caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)
3092-
DC_LOG_BIOS("BIOS EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3091+
if ((info->ext_disp_conn_info.path[i].caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)
3092+
DC_LOG_BIOS("BIOS AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
30933093
else if (bp->base.ctx->dc->config.force_bios_fixed_vs) {
3094-
info->ext_disp_conn_info.path[i].caps |= EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN;
3095-
DC_LOG_BIOS("driver forced EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3094+
info->ext_disp_conn_info.path[i].caps &= ~AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3095+
info->ext_disp_conn_info.path[i].caps |= AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN;
3096+
DC_LOG_BIOS("driver forced AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
30963097
}
30973098
}
30983099
// Log the Checksum and Voltage Swing

‎drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -251,7 +251,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
251251

252252
link_training_settings.lttpr_mode = dp_decide_lttpr_mode(link, &link->cur_link_settings);
253253

254-
if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
254+
if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
255255
link_training_settings.lttpr_mode == LTTPR_MODE_TRANSPARENT)
256256
dp_fixed_vs_pe_read_lane_adjust(
257257
link,
@@ -646,7 +646,7 @@ bool dp_set_test_pattern(
646646
if (IS_DP_PHY_PATTERN(test_pattern)) {
647647
/* Set DPCD Lane Settings before running test pattern */
648648
if (p_link_settings != NULL) {
649-
if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
649+
if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
650650
p_link_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
651651
dp_fixed_vs_pe_set_retimer_lane_settings(
652652
link,

‎drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ static const struct link_hwss dio_fixed_vs_pe_retimer_link_hwss = {
187187

188188
bool requires_fixed_vs_pe_retimer_dio_link_hwss(const struct dc_link *link)
189189
{
190-
return (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN);
190+
return ((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN);
191191
}
192192

193193
const struct link_hwss *get_dio_fixed_vs_pe_retimer_link_hwss(void)

‎drivers/gpu/drm/amd/display/dc/link/link_dpms.c‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1974,8 +1974,8 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
19741974

19751975
if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
19761976
unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
1977-
EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1978-
if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1977+
AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1978+
if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
19791979
/* DP159, Retimer settings */
19801980
eng_id = pipe_ctx->stream_res.stream_enc->id;
19811981

@@ -1986,7 +1986,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
19861986
write_i2c_default_retimer_setting(pipe_ctx,
19871987
is_vga_mode, is_over_340mhz);
19881988
}
1989-
} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1989+
} else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
19901990
/* PI3EQX1204, Redriver settings */
19911991
write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
19921992
}
@@ -2042,7 +2042,7 @@ static enum dc_status enable_link_dp(struct dc_state *state,
20422042
int lt_attempts = LINK_TRAINING_ATTEMPTS;
20432043

20442044
// Increase retry count if attempting DP1.x on FIXED_VS link
2045-
if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
2045+
if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
20462046
link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)
20472047
lt_attempts = 10;
20482048

@@ -2394,21 +2394,21 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
23942394
enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
23952395

23962396
unsigned short masked_chip_caps = link->chip_caps &
2397-
EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2397+
AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
23982398
//Need to inform that sink is going to use legacy HDMI mode.
23992399
write_scdc_data(
24002400
link->ddc,
24012401
165000,//vbios only handles 165Mhz.
24022402
false);
2403-
if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2403+
if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
24042404
/* DP159, Retimer settings */
24052405
if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
24062406
write_i2c_retimer_setting(pipe_ctx,
24072407
false, false, &settings);
24082408
else
24092409
write_i2c_default_retimer_setting(pipe_ctx,
24102410
false, false);
2411-
} else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2411+
} else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
24122412
/* PI3EQX1204, Redriver settings */
24132413
write_i2c_redriver_setting(pipe_ctx, false);
24142414
}

‎drivers/gpu/drm/amd/display/dc/link/link_factory.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -699,7 +699,7 @@ static bool construct_phy(struct dc_link *link,
699699
link->chip_caps);
700700
}
701701

702-
if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
702+
if ((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
703703
link->bios_forced_drive_settings.VOLTAGE_SWING =
704704
(bios->integrated_info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
705705
link->bios_forced_drive_settings.PRE_EMPHASIS =

‎drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -505,7 +505,7 @@ bool try_to_configure_aux_timeout(struct ddc_service *ddc,
505505
bool result = false;
506506
struct ddc *ddc_pin = ddc->ddc_pin;
507507

508-
if ((ddc->link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
508+
if (((ddc->link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
509509
!ddc->link->dc->debug.disable_fixed_vs_aux_timeout_wa &&
510510
ddc->ctx->dce_version == DCN_VERSION_3_1) {
511511
/* Fixed VS workaround for AUX timeout */

‎drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1554,7 +1554,7 @@ enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
15541554

15551555
/* If this chip cap is set, at least one retimer must exist in the chain
15561556
* Override count to 1 if we receive a known bad count (0 or an invalid value) */
1557-
if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1557+
if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
15581558
(dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {
15591559
/* If you see this message consistently, either the host platform has FIXED_VS flag
15601560
* incorrectly configured or the sink device is returning an invalid count.

‎drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ void dp_set_hw_lane_settings(
104104
// Don't return here if using FIXED_VS link HWSS and encoding is 128b/132b
105105
if ((link_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) &&
106106
!is_immediate_downstream(link, offset) &&
107-
(!(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) ||
107+
(!((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) ||
108108
link_dp_get_encoding_format(&link_settings->link_settings) == DP_8b_10b_ENCODING))
109109
return;
110110

‎drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -739,7 +739,7 @@ void override_training_settings(
739739
if (overrides->ffe_preset != NULL)
740740
lt_settings->ffe_preset = overrides->ffe_preset;
741741
/* Override HW lane settings with BIOS forced values if present */
742-
if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
742+
if ((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
743743
lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
744744
lt_settings->voltage_swing = &link->bios_forced_drive_settings.VOLTAGE_SWING;
745745
lt_settings->pre_emphasis = &link->bios_forced_drive_settings.PRE_EMPHASIS;
@@ -1574,7 +1574,7 @@ enum link_training_result dp_perform_link_training(
15741574
* Per DP specs starting from here, DPTX device shall not issue
15751575
* Non-LT AUX transactions inside training mode.
15761576
*/
1577-
if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && encoding == DP_8b_10b_ENCODING)
1577+
if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && encoding == DP_8b_10b_ENCODING)
15781578
status = dp_perform_fixed_vs_pe_training_sequence(link, link_res, &lt_settings);
15791579
else if (encoding == DP_8b_10b_ENCODING)
15801580
status = dp_perform_8b_10b_link_training(link, link_res, &lt_settings);

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