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RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA
We have an implicit set of base behaviors that userspace depends on, which are mostly defined in various ISA specifications. Co-developed-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Evan Green <evan@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com> Link: https://lore.kernel.org/r/20230407231103.2622178-4-evan@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Documentation/riscv/hwprobe.rst

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@@ -39,3 +39,27 @@ The following keys are defined:
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* :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``, as
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defined by the RISC-V privileged architecture specification.
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* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base
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user-visible behavior that this kernel supports. The following base user ABIs
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are defined:
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* :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or
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rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the
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privileged ISA, with the following known exceptions (more exceptions may be
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added, but only if it can be demonstrated that the user ABI is not broken):
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* The :fence.i: instruction cannot be directly executed by userspace
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programs (it may still be executed in userspace via a
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kernel-controlled mechanism such as the vDSO).
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* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions
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that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`:
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base system behavior.
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* :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as
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defined by commit cd20cee ("FMIN/FMAX now implement
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minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
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* :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
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by version 2.2 of the RISC-V ISA manual.

arch/riscv/include/asm/hwprobe.h

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@@ -8,6 +8,6 @@
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#include <uapi/asm/hwprobe.h>
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#define RISCV_HWPROBE_MAX_KEY 2
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#define RISCV_HWPROBE_MAX_KEY 4
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#endif

arch/riscv/include/uapi/asm/hwprobe.h

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@@ -20,6 +20,11 @@ struct riscv_hwprobe {
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#define RISCV_HWPROBE_KEY_MVENDORID 0
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#define RISCV_HWPROBE_KEY_MARCHID 1
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#define RISCV_HWPROBE_KEY_MIMPID 2
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#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
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#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
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#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
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#define RISCV_HWPROBE_IMA_FD (1 << 0)
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#define RISCV_HWPROBE_IMA_C (1 << 1)
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/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
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#endif

arch/riscv/kernel/sys_riscv.c

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#include <asm/cacheflush.h>
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#include <asm/hwprobe.h>
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#include <asm/sbi.h>
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#include <asm/switch_to.h>
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#include <asm/uaccess.h>
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#include <asm/unistd.h>
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#include <asm-generic/mman-common.h>
@@ -125,6 +126,25 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
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case RISCV_HWPROBE_KEY_MIMPID:
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hwprobe_arch_id(pair, cpus);
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break;
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/*
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* The kernel already assumes that the base single-letter ISA
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* extensions are supported on all harts, and only supports the
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* IMA base, so just cheat a bit here and tell that to
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* userspace.
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*/
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case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
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pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
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break;
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case RISCV_HWPROBE_KEY_IMA_EXT_0:
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pair->value = 0;
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if (has_fpu())
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pair->value |= RISCV_HWPROBE_IMA_FD;
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if (riscv_isa_extension_available(NULL, c))
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pair->value |= RISCV_HWPROBE_IMA_C;
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break;
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/*
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* For forward compatibility, unknown keys don't fail the whole

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