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Merge tag 'mmc-v5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
Pull MMC host fixes from Ulf Hansson: - Fix SD-card detection on Intel NUC10i3FNK4 (GL9755) - Replace WARN_ONCE with dev_warn_once for scatterlist offsets - Extend check of scatterlist size alignment with SD_IO_RW_EXTENDED * tag 'mmc-v5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci-pci-gli: increase 1.8V regulator wait mmc: meson-gx: also check SD_IO_RW_EXTENDED for scatterlist size alignment mmc: meson-gx: make replace WARN_ONCE with dev_warn_once about scatterlist offset alignment
2 parents 5328bf8 + a1149a6 commit 011ff61

2 files changed

Lines changed: 11 additions & 3 deletions

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drivers/mmc/host/meson-gx-mmc.c

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -236,7 +236,8 @@ static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
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if (host->dram_access_quirk)
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return;
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239-
if (data->blocks > 1) {
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/* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */
240+
if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) {
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/*
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* In block mode DMA descriptor format, "length" field indicates
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* number of blocks and there is no way to pass DMA size that
@@ -258,7 +259,9 @@ static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
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for_each_sg(data->sg, sg, data->sg_len, i) {
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/* check for 8 byte alignment */
260261
if (sg->offset % 8) {
261-
WARN_ONCE(1, "unaligned scatterlist buffer\n");
262+
dev_warn_once(mmc_dev(mmc),
263+
"unaligned sg offset %u, disabling descriptor DMA for transfer\n",
264+
sg->offset);
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return;
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}
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}

drivers/mmc/host/sdhci-pci-gli.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -627,8 +627,13 @@ static void sdhci_gli_voltage_switch(struct sdhci_host *host)
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*
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* Wait 5ms after set 1.8V signal enable in Host Control 2 register
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* to ensure 1.8V signal enable bit is set by GL9750/GL9755.
630+
*
631+
* ...however, the controller in the NUC10i3FNK4 (a 9755) requires
632+
* slightly longer than 5ms before the control register reports that
633+
* 1.8V is ready, and far longer still before the card will actually
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* work reliably.
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*/
631-
usleep_range(5000, 5500);
636+
usleep_range(100000, 110000);
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}
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634639
static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)

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