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Commit 0136f58

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Evan Quanalexdeucher
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drm/amd/pm: correct UMD pstate clocks for Dimgrey Cavefish and Beige Goby
Correct the UMD pstate profiling clocks for Dimgrey Cavefish and Beige Goby. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 754e0b0 commit 0136f58

2 files changed

Lines changed: 29 additions & 5 deletions

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drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

Lines changed: 21 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1238,21 +1238,37 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
12381238
&dpm_context->dpm_tables.soc_table;
12391239
struct smu_umd_pstate_table *pstate_table =
12401240
&smu->pstate_table;
1241+
struct amdgpu_device *adev = smu->adev;
12411242

12421243
pstate_table->gfxclk_pstate.min = gfx_table->min;
12431244
pstate_table->gfxclk_pstate.peak = gfx_table->max;
1244-
if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1245-
pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
12461245

12471246
pstate_table->uclk_pstate.min = mem_table->min;
12481247
pstate_table->uclk_pstate.peak = mem_table->max;
1249-
if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1250-
pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
12511248

12521249
pstate_table->socclk_pstate.min = soc_table->min;
12531250
pstate_table->socclk_pstate.peak = soc_table->max;
1254-
if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1251+
1252+
switch (adev->asic_type) {
1253+
case CHIP_SIENNA_CICHLID:
1254+
case CHIP_NAVY_FLOUNDER:
1255+
pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1256+
pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
12551257
pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1258+
break;
1259+
case CHIP_DIMGREY_CAVEFISH:
1260+
pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1261+
pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1262+
pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1263+
break;
1264+
case CHIP_BEIGE_GOBY:
1265+
pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1266+
pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1267+
pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1268+
break;
1269+
default:
1270+
break;
1271+
}
12561272

12571273
return 0;
12581274
}

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,14 @@ typedef enum {
3333
#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK 960
3434
#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK 1000
3535

36+
#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK 1950
37+
#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK 960
38+
#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK 676
39+
40+
#define BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK 2200
41+
#define BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK 960
42+
#define BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK 1000
43+
3644
extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);
3745

3846
#endif

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