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Hans HuAndi Shyti
Hans Hu
authored and
Andi Shyti
committed
i2c: wmt: rename something
1. The I2C IP for both wmt and zhaoxin originates from VIA. Rename common registers, functions, and variable names to follow the VIAI2C_ and viai2c_ naming conventions for consistency and clarity. 2. rename i2c_dev to i2c, to shorten the length of a line. 3. rename wait_result to time_left, make it better to reflect the meaning of the value returned by wait_for_completion_timeout(). 4. remove TCR_MASTER_WRITE, its value is 0. Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Hans Hu <hanshu-oc@zhaoxin.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
1 parent 5acd48f commit 013fa16

3 files changed

Lines changed: 143 additions & 146 deletions

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‎drivers/i2c/busses/i2c-viai2c-common.c‎

Lines changed: 78 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -2,14 +2,14 @@
22
#include <linux/of_irq.h>
33
#include "i2c-viai2c-common.h"
44

5-
int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
5+
int viai2c_wait_bus_not_busy(struct viai2c *i2c)
66
{
77
unsigned long timeout;
88

9-
timeout = jiffies + WMT_I2C_TIMEOUT;
10-
while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
9+
timeout = jiffies + VIAI2C_TIMEOUT;
10+
while (!(readw(i2c->base + VIAI2C_REG_CSR) & VIAI2C_CSR_READY_MASK)) {
1111
if (time_after(jiffies, timeout)) {
12-
dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
12+
dev_warn(i2c->dev, "timeout waiting for bus ready\n");
1313
return -EBUSY;
1414
}
1515
msleep(20);
@@ -18,28 +18,28 @@ int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
1818
return 0;
1919
}
2020

21-
int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
21+
int viai2c_check_status(struct viai2c *i2c)
2222
{
2323
int ret = 0;
24-
unsigned long wait_result;
24+
unsigned long time_left;
2525

26-
wait_result = wait_for_completion_timeout(&i2c_dev->complete,
27-
msecs_to_jiffies(500));
28-
if (!wait_result)
26+
time_left = wait_for_completion_timeout(&i2c->complete,
27+
msecs_to_jiffies(500));
28+
if (!time_left)
2929
return -ETIMEDOUT;
3030

31-
if (i2c_dev->cmd_status & ISR_NACK_ADDR)
31+
if (i2c->cmd_status & VIAI2C_ISR_NACK_ADDR)
3232
ret = -EIO;
3333

34-
if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
34+
if (i2c->cmd_status & VIAI2C_ISR_SCL_TIMEOUT)
3535
ret = -ETIMEDOUT;
3636

3737
return ret;
3838
}
3939

40-
static int wmt_i2c_write(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg, int last)
40+
static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last)
4141
{
42-
u16 val, tcr_val = i2c_dev->tcr;
42+
u16 val, tcr_val = i2c->tcr;
4343
int ret;
4444
int xfer_len = 0;
4545

@@ -49,173 +49,172 @@ static int wmt_i2c_write(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg, int
4949
* start at -1 and break out early from the loop
5050
*/
5151
xfer_len = -1;
52-
writew(0, i2c_dev->base + REG_CDR);
52+
writew(0, i2c->base + VIAI2C_REG_CDR);
5353
} else {
54-
writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
54+
writew(pmsg->buf[0] & 0xFF, i2c->base + VIAI2C_REG_CDR);
5555
}
5656

5757
if (!(pmsg->flags & I2C_M_NOSTART)) {
58-
val = readw(i2c_dev->base + REG_CR);
59-
val &= ~CR_TX_END;
60-
val |= CR_CPU_RDY;
61-
writew(val, i2c_dev->base + REG_CR);
58+
val = readw(i2c->base + VIAI2C_REG_CR);
59+
val &= ~VIAI2C_CR_TX_END;
60+
val |= VIAI2C_CR_CPU_RDY;
61+
writew(val, i2c->base + VIAI2C_REG_CR);
6262
}
6363

64-
reinit_completion(&i2c_dev->complete);
64+
reinit_completion(&i2c->complete);
6565

66-
tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
66+
tcr_val |= pmsg->addr & VIAI2C_TCR_ADDR_MASK;
6767

68-
writew(tcr_val, i2c_dev->base + REG_TCR);
68+
writew(tcr_val, i2c->base + VIAI2C_REG_TCR);
6969

7070
if (pmsg->flags & I2C_M_NOSTART) {
71-
val = readw(i2c_dev->base + REG_CR);
72-
val |= CR_CPU_RDY;
73-
writew(val, i2c_dev->base + REG_CR);
71+
val = readw(i2c->base + VIAI2C_REG_CR);
72+
val |= VIAI2C_CR_CPU_RDY;
73+
writew(val, i2c->base + VIAI2C_REG_CR);
7474
}
7575

7676
while (xfer_len < pmsg->len) {
77-
ret = wmt_check_status(i2c_dev);
77+
ret = viai2c_check_status(i2c);
7878
if (ret)
7979
return ret;
8080

8181
xfer_len++;
8282

83-
val = readw(i2c_dev->base + REG_CSR);
84-
if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
85-
dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
83+
val = readw(i2c->base + VIAI2C_REG_CSR);
84+
if (val & VIAI2C_CSR_RCV_NOT_ACK) {
85+
dev_dbg(i2c->dev, "write RCV NACK error\n");
8686
return -EIO;
8787
}
8888

8989
if (pmsg->len == 0) {
90-
val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
91-
writew(val, i2c_dev->base + REG_CR);
90+
val = VIAI2C_CR_TX_END | VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE;
91+
writew(val, i2c->base + VIAI2C_REG_CR);
9292
break;
9393
}
9494

9595
if (xfer_len == pmsg->len) {
9696
if (last != 1)
97-
writew(CR_ENABLE, i2c_dev->base + REG_CR);
97+
writew(VIAI2C_CR_ENABLE, i2c->base + VIAI2C_REG_CR);
9898
} else {
99-
writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
100-
REG_CDR);
101-
writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
99+
writew(pmsg->buf[xfer_len] & 0xFF, i2c->base + VIAI2C_REG_CDR);
100+
writew(VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE, i2c->base + VIAI2C_REG_CR);
102101
}
103102
}
104103

105104
return 0;
106105
}
107106

108-
static int wmt_i2c_read(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg)
107+
static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg)
109108
{
110-
u16 val, tcr_val = i2c_dev->tcr;
109+
u16 val, tcr_val = i2c->tcr;
111110
int ret;
112111
u32 xfer_len = 0;
113112

114-
val = readw(i2c_dev->base + REG_CR);
115-
val &= ~(CR_TX_END | CR_TX_NEXT_NO_ACK);
113+
val = readw(i2c->base + VIAI2C_REG_CR);
114+
val &= ~(VIAI2C_CR_TX_END | VIAI2C_CR_RX_END);
116115

117116
if (!(pmsg->flags & I2C_M_NOSTART))
118-
val |= CR_CPU_RDY;
117+
val |= VIAI2C_CR_CPU_RDY;
119118

120119
if (pmsg->len == 1)
121-
val |= CR_TX_NEXT_NO_ACK;
120+
val |= VIAI2C_CR_RX_END;
122121

123-
writew(val, i2c_dev->base + REG_CR);
122+
writew(val, i2c->base + VIAI2C_REG_CR);
124123

125-
reinit_completion(&i2c_dev->complete);
124+
reinit_completion(&i2c->complete);
126125

127-
tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
126+
tcr_val |= VIAI2C_TCR_READ | (pmsg->addr & VIAI2C_TCR_ADDR_MASK);
128127

129-
writew(tcr_val, i2c_dev->base + REG_TCR);
128+
writew(tcr_val, i2c->base + VIAI2C_REG_TCR);
130129

131130
if (pmsg->flags & I2C_M_NOSTART) {
132-
val = readw(i2c_dev->base + REG_CR);
133-
val |= CR_CPU_RDY;
134-
writew(val, i2c_dev->base + REG_CR);
131+
val = readw(i2c->base + VIAI2C_REG_CR);
132+
val |= VIAI2C_CR_CPU_RDY;
133+
writew(val, i2c->base + VIAI2C_REG_CR);
135134
}
136135

137136
while (xfer_len < pmsg->len) {
138-
ret = wmt_check_status(i2c_dev);
137+
ret = viai2c_check_status(i2c);
139138
if (ret)
140139
return ret;
141140

142-
pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
141+
pmsg->buf[xfer_len] = readw(i2c->base + VIAI2C_REG_CDR) >> 8;
143142
xfer_len++;
144143

145-
val = readw(i2c_dev->base + REG_CR) | CR_CPU_RDY;
144+
val = readw(i2c->base + VIAI2C_REG_CR) | VIAI2C_CR_CPU_RDY;
146145
if (xfer_len == pmsg->len - 1)
147-
val |= CR_TX_NEXT_NO_ACK;
148-
writew(val, i2c_dev->base + REG_CR);
146+
val |= VIAI2C_CR_RX_END;
147+
writew(val, i2c->base + VIAI2C_REG_CR);
149148
}
150149

151150
return 0;
152151
}
153152

154-
int wmt_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
153+
int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
155154
{
156155
struct i2c_msg *pmsg;
157156
int i;
158157
int ret = 0;
159-
struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
158+
struct viai2c *i2c = i2c_get_adapdata(adap);
160159

161160
for (i = 0; ret >= 0 && i < num; i++) {
162161
pmsg = &msgs[i];
163162
if (!(pmsg->flags & I2C_M_NOSTART)) {
164-
ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
163+
ret = viai2c_wait_bus_not_busy(i2c);
165164
if (ret < 0)
166165
return ret;
167166
}
168167

169168
if (pmsg->flags & I2C_M_RD)
170-
ret = wmt_i2c_read(i2c_dev, pmsg);
169+
ret = viai2c_read(i2c, pmsg);
171170
else
172-
ret = wmt_i2c_write(i2c_dev, pmsg, (i + 1) == num);
171+
ret = viai2c_write(i2c, pmsg, (i + 1) == num);
173172
}
174173

175174
return (ret < 0) ? ret : i;
176175
}
177176

178-
static irqreturn_t wmt_i2c_isr(int irq, void *data)
177+
static irqreturn_t viai2c_isr(int irq, void *data)
179178
{
180-
struct wmt_i2c_dev *i2c_dev = data;
179+
struct viai2c *i2c = data;
181180

182181
/* save the status and write-clear it */
183-
i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
184-
writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
182+
i2c->cmd_status = readw(i2c->base + VIAI2C_REG_ISR);
183+
writew(i2c->cmd_status, i2c->base + VIAI2C_REG_ISR);
185184

186-
complete(&i2c_dev->complete);
185+
complete(&i2c->complete);
187186

188187
return IRQ_HANDLED;
189188
}
190189

191-
int wmt_i2c_init(struct platform_device *pdev, struct wmt_i2c_dev **pi2c_dev)
190+
int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c)
192191
{
193192
int err;
194-
struct wmt_i2c_dev *i2c_dev;
193+
struct viai2c *i2c;
195194
struct device_node *np = pdev->dev.of_node;
196195

197-
i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
198-
if (!i2c_dev)
196+
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
197+
if (!i2c)
199198
return -ENOMEM;
200199

201-
i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
202-
if (IS_ERR(i2c_dev->base))
203-
return PTR_ERR(i2c_dev->base);
200+
i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
201+
if (IS_ERR(i2c->base))
202+
return PTR_ERR(i2c->base);
204203

205-
i2c_dev->irq = irq_of_parse_and_map(np, 0);
206-
if (!i2c_dev->irq)
204+
i2c->irq = irq_of_parse_and_map(np, 0);
205+
if (!i2c->irq)
207206
return -EINVAL;
208207

209-
err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr,
210-
0, pdev->name, i2c_dev);
208+
err = devm_request_irq(&pdev->dev, i2c->irq, viai2c_isr,
209+
0, pdev->name, i2c);
211210
if (err)
212211
return dev_err_probe(&pdev->dev, err,
213-
"failed to request irq %i\n", i2c_dev->irq);
212+
"failed to request irq %i\n", i2c->irq);
214213

215-
i2c_dev->dev = &pdev->dev;
216-
init_completion(&i2c_dev->complete);
217-
platform_set_drvdata(pdev, i2c_dev);
214+
i2c->dev = &pdev->dev;
215+
init_completion(&i2c->complete);
216+
platform_set_drvdata(pdev, i2c);
218217

219-
*pi2c_dev = i2c_dev;
218+
*pi2c = i2c;
220219
return 0;
221220
}

‎drivers/i2c/busses/i2c-viai2c-common.h‎

Lines changed: 34 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -11,48 +11,46 @@
1111
#include <linux/of_irq.h>
1212
#include <linux/platform_device.h>
1313

14-
#define REG_CR 0x00
15-
#define REG_TCR 0x02
16-
#define REG_CSR 0x04
17-
#define REG_ISR 0x06
18-
#define REG_IMR 0x08
19-
#define REG_CDR 0x0A
20-
#define REG_TR 0x0C
21-
#define REG_MCR 0x0E
22-
2314
/* REG_CR Bit fields */
24-
#define CR_TX_NEXT_ACK 0x0000
25-
#define CR_ENABLE 0x0001
26-
#define CR_TX_NEXT_NO_ACK 0x0002
27-
#define CR_TX_END 0x0004
28-
#define CR_CPU_RDY 0x0008
29-
#define SLAV_MODE_SEL 0x8000
15+
#define VIAI2C_REG_CR 0x00
16+
#define VIAI2C_CR_ENABLE BIT(0)
17+
#define VIAI2C_CR_RX_END BIT(1)
18+
#define VIAI2C_CR_TX_END BIT(2)
19+
#define VIAI2C_CR_CPU_RDY BIT(3)
20+
#define VIAI2C_CR_END_MASK GENMASK(2, 1)
3021

3122
/* REG_TCR Bit fields */
32-
#define TCR_STANDARD_MODE 0x0000
33-
#define TCR_MASTER_WRITE 0x0000
34-
#define TCR_HS_MODE 0x2000
35-
#define TCR_MASTER_READ 0x4000
36-
#define TCR_FAST_MODE 0x8000
37-
#define TCR_SLAVE_ADDR_MASK 0x007F
23+
#define VIAI2C_REG_TCR 0x02
24+
#define VIAI2C_TCR_HS_MODE BIT(13)
25+
#define VIAI2C_TCR_READ BIT(14)
26+
#define VIAI2C_TCR_FAST BIT(15)
27+
#define VIAI2C_TCR_ADDR_MASK GENMASK(6, 0)
28+
29+
/* REG_CSR Bit fields */
30+
#define VIAI2C_REG_CSR 0x04
31+
#define VIAI2C_CSR_RCV_NOT_ACK BIT(0)
32+
#define VIAI2C_CSR_RCV_ACK_MASK BIT(0)
33+
#define VIAI2C_CSR_READY_MASK BIT(1)
3834

3935
/* REG_ISR Bit fields */
40-
#define ISR_NACK_ADDR 0x0001
41-
#define ISR_BYTE_END 0x0002
42-
#define ISR_SCL_TIMEOUT 0x0004
43-
#define ISR_WRITE_ALL 0x0007
36+
#define VIAI2C_REG_ISR 0x06
37+
#define VIAI2C_ISR_NACK_ADDR BIT(0)
38+
#define VIAI2C_ISR_BYTE_END BIT(1)
39+
#define VIAI2C_ISR_SCL_TIMEOUT BIT(2)
40+
#define VIAI2C_ISR_MASK_ALL GENMASK(2, 0)
4441

4542
/* REG_IMR Bit fields */
46-
#define IMR_ENABLE_ALL 0x0007
43+
#define VIAI2C_REG_IMR 0x08
44+
#define VIAI2C_IMR_BYTE BIT(1)
45+
#define VIAI2C_IMR_ENABLE_ALL GENMASK(2, 0)
4746

48-
/* REG_CSR Bit fields */
49-
#define CSR_RCV_NOT_ACK 0x0001
50-
#define CSR_RCV_ACK_MASK 0x0001
51-
#define CSR_READY_MASK 0x0002
47+
#define VIAI2C_REG_CDR 0x0A
48+
#define VIAI2C_REG_TR 0x0C
49+
#define VIAI2C_REG_MCR 0x0E
5250

53-
#define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000))
51+
#define VIAI2C_TIMEOUT (msecs_to_jiffies(1000))
5452

55-
struct wmt_i2c_dev {
53+
struct viai2c {
5654
struct i2c_adapter adapter;
5755
struct completion complete;
5856
struct device *dev;
@@ -63,9 +61,9 @@ struct wmt_i2c_dev {
6361
u16 cmd_status;
6462
};
6563

66-
int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev);
67-
int wmt_check_status(struct wmt_i2c_dev *i2c_dev);
68-
int wmt_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num);
69-
int wmt_i2c_init(struct platform_device *pdev, struct wmt_i2c_dev **pi2c_dev);
64+
int viai2c_wait_bus_not_busy(struct viai2c *i2c);
65+
int viai2c_check_status(struct viai2c *i2c);
66+
int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num);
67+
int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c);
7068

7169
#endif

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