Skip to content

Commit 015e705

Browse files
mszyprowSylwester Nawrocki
mszyprow
authored and
Sylwester Nawrocki
committed
clk: samsung: remove __clk_lookup() usage
__clk_lookup() interface is obsolete, so remove it from the Samsung clock drivers. This has been achieved by getting rid of custom _get_rate() helper and replacing it with clk_hw_get_rate(). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211018125456.8292-2-m.szyprowski@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
1 parent d68f50e commit 015e705

8 files changed

Lines changed: 32 additions & 36 deletions

File tree

‎drivers/clk/samsung/clk-exynos4.c‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -437,7 +437,7 @@ static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
437437

438438
/* list of mux clocks supported in exynos4210 soc */
439439
static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
440-
MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
440+
MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
441441
};
442442

443443
static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
@@ -603,7 +603,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
603603
DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
604604
DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
605605
DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
606-
DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
606+
DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
607607
DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
608608
DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
609609
DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
@@ -1254,21 +1254,21 @@ static void __init exynos4_clk_init(struct device_node *np,
12541254
samsung_clk_register_mux(ctx, exynos4210_mux_early,
12551255
ARRAY_SIZE(exynos4210_mux_early));
12561256

1257-
if (_get_rate("fin_pll") == 24000000) {
1257+
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
12581258
exynos4210_plls[apll].rate_table =
12591259
exynos4210_apll_rates;
12601260
exynos4210_plls[epll].rate_table =
12611261
exynos4210_epll_rates;
12621262
}
12631263

1264-
if (_get_rate("mout_vpllsrc") == 24000000)
1264+
if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000)
12651265
exynos4210_plls[vpll].rate_table =
12661266
exynos4210_vpll_rates;
12671267

12681268
samsung_clk_register_pll(ctx, exynos4210_plls,
12691269
ARRAY_SIZE(exynos4210_plls), reg_base);
12701270
} else {
1271-
if (_get_rate("fin_pll") == 24000000) {
1271+
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
12721272
exynos4x12_plls[apll].rate_table =
12731273
exynos4x12_apll_rates;
12741274
exynos4x12_plls[epll].rate_table =
@@ -1344,9 +1344,11 @@ static void __init exynos4_clk_init(struct device_node *np,
13441344
pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
13451345
"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
13461346
exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1347-
_get_rate("sclk_apll"), _get_rate("sclk_mpll"),
1348-
_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
1349-
_get_rate("div_core2"));
1347+
clk_hw_get_rate(hws[CLK_SCLK_APLL]),
1348+
clk_hw_get_rate(hws[CLK_SCLK_MPLL]),
1349+
clk_hw_get_rate(hws[CLK_SCLK_EPLL]),
1350+
clk_hw_get_rate(hws[CLK_SCLK_VPLL]),
1351+
clk_hw_get_rate(hws[CLK_DIV_CORE2]));
13501352
}
13511353

13521354

‎drivers/clk/samsung/clk-exynos5250.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,7 @@ static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __
239239
};
240240

241241
static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
242-
MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
242+
MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
243243
};
244244

245245
static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
@@ -351,7 +351,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
351351
*/
352352
DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
353353
DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
354-
DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
354+
DIV(CLK_DIV_ARM2, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
355355

356356
/*
357357
* CMU_TOP
@@ -801,12 +801,12 @@ static void __init exynos5250_clk_init(struct device_node *np)
801801
samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
802802
ARRAY_SIZE(exynos5250_pll_pmux_clks));
803803

804-
if (_get_rate("fin_pll") == 24 * MHZ) {
804+
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
805805
exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
806806
exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
807807
}
808808

809-
if (_get_rate("mout_vpllsrc") == 24 * MHZ)
809+
if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ)
810810
exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
811811

812812
samsung_clk_register_pll(ctx, exynos5250_plls,
@@ -855,6 +855,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
855855
samsung_clk_of_add_provider(np, ctx);
856856

857857
pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
858-
_get_rate("div_arm2"));
858+
clk_hw_get_rate(hws[CLK_DIV_ARM2]));
859859
}
860860
CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);

‎drivers/clk/samsung/clk-exynos5420.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1580,7 +1580,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
15801580
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
15811581
ext_clk_match);
15821582

1583-
if (_get_rate("fin_pll") == 24 * MHZ) {
1583+
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
15841584
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
15851585
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
15861586
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;

‎drivers/clk/samsung/clk-s3c2410.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -323,6 +323,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
323323
void __iomem *base)
324324
{
325325
struct samsung_clk_provider *ctx;
326+
struct clk_hw **hws;
326327
reg_base = base;
327328

328329
if (np) {
@@ -332,13 +333,14 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
332333
}
333334

334335
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
336+
hws = ctx->clk_data.hws;
335337

336338
/* Register external clocks only in non-dt cases */
337339
if (!np)
338340
s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
339341

340342
if (current_soc == S3C2410) {
341-
if (_get_rate("xti") == 12 * MHZ) {
343+
if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
342344
s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
343345
s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
344346
}
@@ -348,7 +350,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
348350
ARRAY_SIZE(s3c2410_plls), reg_base);
349351

350352
} else { /* S3C2440, S3C2442 */
351-
if (_get_rate("xti") == 12 * MHZ) {
353+
if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
352354
/*
353355
* plls follow different calculation schemes, with the
354356
* upll following the same scheme as the s3c2410 plls

‎drivers/clk/samsung/clk-s3c64xx.c‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -394,6 +394,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
394394
void __iomem *base)
395395
{
396396
struct samsung_clk_provider *ctx;
397+
struct clk_hw **hws;
397398

398399
reg_base = base;
399400
is_s3c6400 = s3c6400;
@@ -405,6 +406,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
405406
}
406407

407408
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
409+
hws = ctx->clk_data.hws;
408410

409411
/* Register external clocks. */
410412
if (!np)
@@ -459,8 +461,10 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
459461
pr_info("%s clocks: apll = %lu, mpll = %lu\n"
460462
"\tepll = %lu, arm_clk = %lu\n",
461463
is_s3c6400 ? "S3C6400" : "S3C6410",
462-
_get_rate("fout_apll"), _get_rate("fout_mpll"),
463-
_get_rate("fout_epll"), _get_rate("armclk"));
464+
clk_hw_get_rate(hws[MOUT_APLL]),
465+
clk_hw_get_rate(hws[MOUT_MPLL]),
466+
clk_hw_get_rate(hws[MOUT_EPLL]),
467+
clk_hw_get_rate(hws[ARMCLK]));
464468
}
465469

466470
static void __init s3c6400_clk_init(struct device_node *np)

‎drivers/clk/samsung/clk-s5pv210.c‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -741,8 +741,10 @@ static void __init __s5pv210_clk_init(struct device_node *np,
741741
bool is_s5p6442)
742742
{
743743
struct samsung_clk_provider *ctx;
744+
struct clk_hw **hws;
744745

745746
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
747+
hws = ctx->clk_data.hws;
746748

747749
samsung_clk_register_mux(ctx, early_mux_clks,
748750
ARRAY_SIZE(early_mux_clks));
@@ -789,8 +791,10 @@ static void __init __s5pv210_clk_init(struct device_node *np,
789791
pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
790792
"\tmout_epll = %ld, mout_vpll = %ld\n",
791793
is_s5p6442 ? "S5P6442" : "S5PV210",
792-
_get_rate("mout_apll"), _get_rate("mout_mpll"),
793-
_get_rate("mout_epll"), _get_rate("mout_vpll"));
794+
clk_hw_get_rate(hws[MOUT_APLL]),
795+
clk_hw_get_rate(hws[MOUT_MPLL]),
796+
clk_hw_get_rate(hws[MOUT_EPLL]),
797+
clk_hw_get_rate(hws[MOUT_VPLL]));
794798
}
795799

796800
static void __init s5pv210_clk_dt_init(struct device_node *np)

‎drivers/clk/samsung/clk.c‎

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -268,20 +268,6 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
268268
samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
269269
}
270270

271-
/* utility function to get the rate of a specified clock */
272-
unsigned long _get_rate(const char *clk_name)
273-
{
274-
struct clk *clk;
275-
276-
clk = __clk_lookup(clk_name);
277-
if (!clk) {
278-
pr_err("%s: could not find clock %s\n", __func__, clk_name);
279-
return 0;
280-
}
281-
282-
return clk_get_rate(clk);
283-
}
284-
285271
#ifdef CONFIG_PM_SLEEP
286272
static int samsung_clk_suspend(void)
287273
{

‎drivers/clk/samsung/clk.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -381,8 +381,6 @@ extern struct samsung_clk_provider __init *samsung_cmu_register_one(
381381
struct device_node *,
382382
const struct samsung_cmu_info *);
383383

384-
extern unsigned long _get_rate(const char *clk_name);
385-
386384
#ifdef CONFIG_PM_SLEEP
387385
extern void samsung_clk_extended_sleep_init(void __iomem *reg_base,
388386
const unsigned long *rdump,

0 commit comments

Comments
 (0)