@@ -602,7 +602,7 @@ u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
602602 if (amdgpu_device_skip_hw_access (adev ))
603603 return 0 ;
604604
605- if (index < adev -> doorbell .num_doorbells ) {
605+ if (index < adev -> doorbell .num_kernel_doorbells ) {
606606 return readl (adev -> doorbell .ptr + index );
607607 } else {
608608 DRM_ERROR ("reading beyond doorbell aperture: 0x%08x!\n" , index );
@@ -625,7 +625,7 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
625625 if (amdgpu_device_skip_hw_access (adev ))
626626 return ;
627627
628- if (index < adev -> doorbell .num_doorbells ) {
628+ if (index < adev -> doorbell .num_kernel_doorbells ) {
629629 writel (v , adev -> doorbell .ptr + index );
630630 } else {
631631 DRM_ERROR ("writing beyond doorbell aperture: 0x%08x!\n" , index );
@@ -646,7 +646,7 @@ u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
646646 if (amdgpu_device_skip_hw_access (adev ))
647647 return 0 ;
648648
649- if (index < adev -> doorbell .num_doorbells ) {
649+ if (index < adev -> doorbell .num_kernel_doorbells ) {
650650 return atomic64_read ((atomic64_t * )(adev -> doorbell .ptr + index ));
651651 } else {
652652 DRM_ERROR ("reading beyond doorbell aperture: 0x%08x!\n" , index );
@@ -669,7 +669,7 @@ void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
669669 if (amdgpu_device_skip_hw_access (adev ))
670670 return ;
671671
672- if (index < adev -> doorbell .num_doorbells ) {
672+ if (index < adev -> doorbell .num_kernel_doorbells ) {
673673 atomic64_set ((atomic64_t * )(adev -> doorbell .ptr + index ), v );
674674 } else {
675675 DRM_ERROR ("writing beyond doorbell aperture: 0x%08x!\n" , index );
@@ -1060,7 +1060,7 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
10601060 if (adev -> asic_type < CHIP_BONAIRE ) {
10611061 adev -> doorbell .base = 0 ;
10621062 adev -> doorbell .size = 0 ;
1063- adev -> doorbell .num_doorbells = 0 ;
1063+ adev -> doorbell .num_kernel_doorbells = 0 ;
10641064 adev -> doorbell .ptr = NULL ;
10651065 return 0 ;
10661066 }
@@ -1075,27 +1075,27 @@ static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
10751075 adev -> doorbell .size = pci_resource_len (adev -> pdev , 2 );
10761076
10771077 if (adev -> enable_mes ) {
1078- adev -> doorbell .num_doorbells =
1078+ adev -> doorbell .num_kernel_doorbells =
10791079 adev -> doorbell .size / sizeof (u32 );
10801080 } else {
1081- adev -> doorbell .num_doorbells =
1081+ adev -> doorbell .num_kernel_doorbells =
10821082 min_t (u32 , adev -> doorbell .size / sizeof (u32 ),
10831083 adev -> doorbell_index .max_assignment + 1 );
1084- if (adev -> doorbell .num_doorbells == 0 )
1084+ if (adev -> doorbell .num_kernel_doorbells == 0 )
10851085 return - EINVAL ;
10861086
10871087 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
10881088 * paging queue doorbell use the second page. The
10891089 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
10901090 * doorbells are in the first page. So with paging queue enabled,
1091- * the max num_doorbells should + 1 page (0x400 in dword)
1091+ * the max num_kernel_doorbells should + 1 page (0x400 in dword)
10921092 */
10931093 if (adev -> asic_type >= CHIP_VEGA10 )
1094- adev -> doorbell .num_doorbells += 0x400 ;
1094+ adev -> doorbell .num_kernel_doorbells += 0x400 ;
10951095 }
10961096
10971097 adev -> doorbell .ptr = ioremap (adev -> doorbell .base ,
1098- adev -> doorbell .num_doorbells *
1098+ adev -> doorbell .num_kernel_doorbells *
10991099 sizeof (u32 ));
11001100 if (adev -> doorbell .ptr == NULL )
11011101 return - ENOMEM ;
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