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soc/tegra: pmc: Store PMC context in clocks
Clocks exposed by the PMC need to reference the PMC context for register programming. Store a reference to the context in the data structure for each clock to avoid the need for a global variable. Signed-off-by: Thierry Reding <treding@nvidia.com>
1 parent 1c67294 commit 0732dff

1 file changed

Lines changed: 26 additions & 20 deletions

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drivers/soc/tegra/pmc.c

Lines changed: 26 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -202,18 +202,20 @@
202202
#define TEGRA_SMC_PMC_WRITE 0xbb
203203

204204
struct pmc_clk {
205-
struct clk_hw hw;
206-
unsigned long offs;
207-
u32 mux_shift;
208-
u32 force_en_shift;
205+
struct clk_hw hw;
206+
struct tegra_pmc *pmc;
207+
unsigned long offs;
208+
u32 mux_shift;
209+
u32 force_en_shift;
209210
};
210211

211212
#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
212213

213214
struct pmc_clk_gate {
214-
struct clk_hw hw;
215-
unsigned long offs;
216-
u32 shift;
215+
struct clk_hw hw;
216+
struct tegra_pmc *pmc;
217+
unsigned long offs;
218+
u32 shift;
217219
};
218220

219221
#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
@@ -2601,7 +2603,7 @@ static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
26012603
return NOTIFY_OK;
26022604
}
26032605

2604-
static void pmc_clk_fence_udelay(u32 offset)
2606+
static void pmc_clk_fence_udelay(struct tegra_pmc *pmc, u32 offset)
26052607
{
26062608
tegra_pmc_readl(pmc, offset);
26072609
/* pmc clk propagation delay 2 us */
@@ -2613,7 +2615,7 @@ static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
26132615
struct pmc_clk *clk = to_pmc_clk(hw);
26142616
u32 val;
26152617

2616-
val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2618+
val = tegra_pmc_readl(clk->pmc, clk->offs) >> clk->mux_shift;
26172619
val &= PMC_CLK_OUT_MUX_MASK;
26182620

26192621
return val;
@@ -2624,11 +2626,11 @@ static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
26242626
struct pmc_clk *clk = to_pmc_clk(hw);
26252627
u32 val;
26262628

2627-
val = tegra_pmc_readl(pmc, clk->offs);
2629+
val = tegra_pmc_readl(clk->pmc, clk->offs);
26282630
val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
26292631
val |= index << clk->mux_shift;
2630-
tegra_pmc_writel(pmc, val, clk->offs);
2631-
pmc_clk_fence_udelay(clk->offs);
2632+
tegra_pmc_writel(clk->pmc, val, clk->offs);
2633+
pmc_clk_fence_udelay(clk->pmc, clk->offs);
26322634

26332635
return 0;
26342636
}
@@ -2638,26 +2640,27 @@ static int pmc_clk_is_enabled(struct clk_hw *hw)
26382640
struct pmc_clk *clk = to_pmc_clk(hw);
26392641
u32 val;
26402642

2641-
val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2643+
val = tegra_pmc_readl(clk->pmc, clk->offs) & BIT(clk->force_en_shift);
26422644

26432645
return val ? 1 : 0;
26442646
}
26452647

2646-
static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2648+
static void pmc_clk_set_state(struct tegra_pmc *pmc, unsigned long offs,
2649+
u32 shift, int state)
26472650
{
26482651
u32 val;
26492652

26502653
val = tegra_pmc_readl(pmc, offs);
26512654
val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
26522655
tegra_pmc_writel(pmc, val, offs);
2653-
pmc_clk_fence_udelay(offs);
2656+
pmc_clk_fence_udelay(pmc, offs);
26542657
}
26552658

26562659
static int pmc_clk_enable(struct clk_hw *hw)
26572660
{
26582661
struct pmc_clk *clk = to_pmc_clk(hw);
26592662

2660-
pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2663+
pmc_clk_set_state(clk->pmc, clk->offs, clk->force_en_shift, 1);
26612664

26622665
return 0;
26632666
}
@@ -2666,7 +2669,7 @@ static void pmc_clk_disable(struct clk_hw *hw)
26662669
{
26672670
struct pmc_clk *clk = to_pmc_clk(hw);
26682671

2669-
pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2672+
pmc_clk_set_state(clk->pmc, clk->offs, clk->force_en_shift, 0);
26702673
}
26712674

26722675
static const struct clk_ops pmc_clk_ops = {
@@ -2698,6 +2701,7 @@ tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
26982701
CLK_SET_PARENT_GATE;
26992702

27002703
pmc_clk->hw.init = &init;
2704+
pmc_clk->pmc = pmc;
27012705
pmc_clk->offs = offset;
27022706
pmc_clk->mux_shift = data->mux_shift;
27032707
pmc_clk->force_en_shift = data->force_en_shift;
@@ -2708,15 +2712,16 @@ tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
27082712
static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
27092713
{
27102714
struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2715+
u32 value = tegra_pmc_readl(gate->pmc, gate->offs);
27112716

2712-
return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2717+
return value & BIT(gate->shift) ? 1 : 0;
27132718
}
27142719

27152720
static int pmc_clk_gate_enable(struct clk_hw *hw)
27162721
{
27172722
struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
27182723

2719-
pmc_clk_set_state(gate->offs, gate->shift, 1);
2724+
pmc_clk_set_state(gate->pmc, gate->offs, gate->shift, 1);
27202725

27212726
return 0;
27222727
}
@@ -2725,7 +2730,7 @@ static void pmc_clk_gate_disable(struct clk_hw *hw)
27252730
{
27262731
struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
27272732

2728-
pmc_clk_set_state(gate->offs, gate->shift, 0);
2733+
pmc_clk_set_state(gate->pmc, gate->offs, gate->shift, 0);
27292734
}
27302735

27312736
static const struct clk_ops pmc_clk_gate_ops = {
@@ -2753,6 +2758,7 @@ tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
27532758
init.flags = 0;
27542759

27552760
gate->hw.init = &init;
2761+
gate->pmc = pmc;
27562762
gate->offs = offset;
27572763
gate->shift = shift;
27582764

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