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Ben Skeggsairlied
Ben Skeggs
authored and
airlied
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drm/nouveau/nvenc/r535: initial support
Adds support for allocating VIDEO_ENCODER classes from RM. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230918202149.4343-43-skeggsb@gmail.com
1 parent 142cd60 commit 08ab88f

13 files changed

Lines changed: 248 additions & 1 deletion

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‎drivers/gpu/drm/nouveau/include/nvif/class.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -231,6 +231,10 @@
231231
#define AMPERE_DMA_COPY_A 0x0000c6b5
232232
#define AMPERE_DMA_COPY_B 0x0000c7b5
233233

234+
#define NVC4B7_VIDEO_ENCODER 0x0000c4b7
235+
#define NVC7B7_VIDEO_ENCODER 0x0000c7b7
236+
#define NVC9B7_VIDEO_ENCODER 0x0000c9b7
237+
234238
#define FERMI_DECOMPRESS 0x000090b8
235239

236240
#define NV50_COMPUTE 0x000050c0

‎drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h‎

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Original file line numberDiff line numberDiff line change
@@ -13,4 +13,6 @@ struct nvkm_nvenc {
1313

1414
int gm107_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);
1515
int tu102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);
16+
int ga102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);
17+
int ad102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);
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#endif

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/nvos.h‎

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Original file line numberDiff line numberDiff line change
@@ -112,6 +112,13 @@ typedef struct
112112
NvU32 engineInstance; // Select NVDEC0 or NVDEC1 or NVDEC2
113113
} NV_BSP_ALLOCATION_PARAMETERS;
114114

115+
typedef struct
116+
{
117+
NvU32 size;
118+
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of MSENC?
119+
NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2
120+
} NV_MSENC_ALLOCATION_PARAMETERS;
121+
115122
typedef struct
116123
{
117124
NvU32 index;

‎drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gpu/intr/engine_idx.h‎

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Original file line numberDiff line numberDiff line change
@@ -32,6 +32,10 @@
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3333
#define MC_ENGINE_IDX_CE9 24
3434

35+
#define MC_ENGINE_IDX_MSENC 38
36+
37+
#define MC_ENGINE_IDX_MSENC2 40
38+
3539
#define MC_ENGINE_IDX_GSP 49
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3741
#define MC_ENGINE_IDX_BSP 64

‎drivers/gpu/drm/nouveau/nvkm/engine/device/base.c‎

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Original file line numberDiff line numberDiff line change
@@ -2622,6 +2622,7 @@ nv172_chipset = {
26222622
.fifo = { 0x00000001, ga102_fifo_new },
26232623
.gr = { 0x00000001, ga102_gr_new },
26242624
.nvdec = { 0x00000003, ga102_nvdec_new },
2625+
.nvenc = { 0x00000001, ga102_nvenc_new },
26252626
.sec2 = { 0x00000001, ga102_sec2_new },
26262627
};
26272628

@@ -2652,6 +2653,7 @@ nv173_chipset = {
26522653
.fifo = { 0x00000001, ga102_fifo_new },
26532654
.gr = { 0x00000001, ga102_gr_new },
26542655
.nvdec = { 0x00000003, ga102_nvdec_new },
2656+
.nvenc = { 0x00000001, ga102_nvenc_new },
26552657
.sec2 = { 0x00000001, ga102_sec2_new },
26562658
};
26572659

@@ -2682,6 +2684,7 @@ nv174_chipset = {
26822684
.fifo = { 0x00000001, ga102_fifo_new },
26832685
.gr = { 0x00000001, ga102_gr_new },
26842686
.nvdec = { 0x00000003, ga102_nvdec_new },
2687+
.nvenc = { 0x00000001, ga102_nvenc_new },
26852688
.sec2 = { 0x00000001, ga102_sec2_new },
26862689
};
26872690

@@ -2712,6 +2715,7 @@ nv176_chipset = {
27122715
.fifo = { 0x00000001, ga102_fifo_new },
27132716
.gr = { 0x00000001, ga102_gr_new },
27142717
.nvdec = { 0x00000003, ga102_nvdec_new },
2718+
.nvenc = { 0x00000001, ga102_nvenc_new },
27152719
.sec2 = { 0x00000001, ga102_sec2_new },
27162720
};
27172721

@@ -2742,6 +2746,7 @@ nv177_chipset = {
27422746
.fifo = { 0x00000001, ga102_fifo_new },
27432747
.gr = { 0x00000001, ga102_gr_new },
27442748
.nvdec = { 0x00000003, ga102_nvdec_new },
2749+
.nvenc = { 0x00000001, ga102_nvenc_new },
27452750
.sec2 = { 0x00000001, ga102_sec2_new },
27462751
};
27472752

@@ -2765,6 +2770,7 @@ nv192_chipset = {
27652770
.fifo = { 0x00000001, ga102_fifo_new },
27662771
.gr = { 0x00000001, ad102_gr_new },
27672772
.nvdec = { 0x0000000f, ad102_nvdec_new },
2773+
.nvenc = { 0x00000007, ad102_nvenc_new },
27682774
.sec2 = { 0x00000001, ga102_sec2_new },
27692775
};
27702776

@@ -2788,6 +2794,7 @@ nv193_chipset = {
27882794
.fifo = { 0x00000001, ga102_fifo_new },
27892795
.gr = { 0x00000001, ad102_gr_new },
27902796
.nvdec = { 0x0000000f, ad102_nvdec_new },
2797+
.nvenc = { 0x00000007, ad102_nvenc_new },
27912798
.sec2 = { 0x00000001, ga102_sec2_new },
27922799
};
27932800

@@ -2811,6 +2818,7 @@ nv194_chipset = {
28112818
.fifo = { 0x00000001, ga102_fifo_new },
28122819
.gr = { 0x00000001, ad102_gr_new },
28132820
.nvdec = { 0x0000000f, ad102_nvdec_new },
2821+
.nvenc = { 0x00000007, ad102_nvenc_new },
28142822
.sec2 = { 0x00000001, ga102_sec2_new },
28152823
};
28162824

@@ -2834,6 +2842,7 @@ nv196_chipset = {
28342842
.fifo = { 0x00000001, ga102_fifo_new },
28352843
.gr = { 0x00000001, ad102_gr_new },
28362844
.nvdec = { 0x0000000f, ad102_nvdec_new },
2845+
.nvenc = { 0x00000007, ad102_nvenc_new },
28372846
.sec2 = { 0x00000001, ga102_sec2_new },
28382847
};
28392848

@@ -2857,6 +2866,7 @@ nv197_chipset = {
28572866
.fifo = { 0x00000001, ga102_fifo_new },
28582867
.gr = { 0x00000001, ad102_gr_new },
28592868
.nvdec = { 0x0000000f, ad102_nvdec_new },
2869+
.nvenc = { 0x00000007, ad102_nvenc_new },
28602870
.sec2 = { 0x00000001, ga102_sec2_new },
28612871
};
28622872

‎drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c‎

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Original file line numberDiff line numberDiff line change
@@ -596,6 +596,7 @@ r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
596596
engn = nvkm_runl_add(runl, nv2080, &r535_gr, type, inst);
597597
break;
598598
case NVKM_ENGINE_NVDEC:
599+
case NVKM_ENGINE_NVENC:
599600
engn = nvkm_runl_add(runl, nv2080, &r535_flcn, type, inst);
600601
break;
601602
case NVKM_ENGINE_SW:

‎drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild‎

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Original file line numberDiff line numberDiff line change
@@ -2,3 +2,7 @@
22
nvkm-y += nvkm/engine/nvenc/base.o
33
nvkm-y += nvkm/engine/nvenc/gm107.o
44
nvkm-y += nvkm/engine/nvenc/tu102.o
5+
nvkm-y += nvkm/engine/nvenc/ga102.o
6+
nvkm-y += nvkm/engine/nvenc/ad102.o
7+
8+
nvkm-y += nvkm/engine/nvenc/r535.o

‎drivers/gpu/drm/nouveau/nvkm/engine/nvenc/ad102.c‎

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@@ -0,0 +1,44 @@
1+
/*
2+
* Copyright 2023 Red Hat Inc.
3+
*
4+
* Permission is hereby granted, free of charge, to any person obtaining a
5+
* copy of this software and associated documentation files (the "Software"),
6+
* to deal in the Software without restriction, including without limitation
7+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+
* and/or sell copies of the Software, and to permit persons to whom the
9+
* Software is furnished to do so, subject to the following conditions:
10+
*
11+
* The above copyright notice and this permission notice shall be included in
12+
* all copies or substantial portions of the Software.
13+
*
14+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+
* OTHER DEALINGS IN THE SOFTWARE.
21+
*/
22+
#include "priv.h"
23+
24+
#include <subdev/gsp.h>
25+
26+
#include <nvif/class.h>
27+
28+
static const struct nvkm_engine_func
29+
ad102_nvenc = {
30+
.sclass = {
31+
{ -1, -1, NVC9B7_VIDEO_ENCODER },
32+
{}
33+
}
34+
};
35+
36+
int
37+
ad102_nvenc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
38+
struct nvkm_nvenc **pnvenc)
39+
{
40+
if (nvkm_gsp_rm(device->gsp))
41+
return r535_nvenc_new(&ad102_nvenc, device, type, inst, pnvenc);
42+
43+
return -ENODEV;
44+
}

‎drivers/gpu/drm/nouveau/nvkm/engine/nvenc/ga102.c‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
1+
/*
2+
* Copyright 2023 Red Hat Inc.
3+
*
4+
* Permission is hereby granted, free of charge, to any person obtaining a
5+
* copy of this software and associated documentation files (the "Software"),
6+
* to deal in the Software without restriction, including without limitation
7+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+
* and/or sell copies of the Software, and to permit persons to whom the
9+
* Software is furnished to do so, subject to the following conditions:
10+
*
11+
* The above copyright notice and this permission notice shall be included in
12+
* all copies or substantial portions of the Software.
13+
*
14+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+
* OTHER DEALINGS IN THE SOFTWARE.
21+
*/
22+
#include "priv.h"
23+
24+
#include <subdev/gsp.h>
25+
26+
#include <nvif/class.h>
27+
28+
static const struct nvkm_engine_func
29+
ga102_nvenc = {
30+
.sclass = {
31+
{ -1, -1, NVC7B7_VIDEO_ENCODER },
32+
{}
33+
}
34+
};
35+
36+
int
37+
ga102_nvenc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
38+
struct nvkm_nvenc **pnvenc)
39+
{
40+
if (nvkm_gsp_rm(device->gsp))
41+
return r535_nvenc_new(&ga102_nvenc, device, type, inst, pnvenc);
42+
43+
return -ENODEV;
44+
}

‎drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h‎

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Original file line numberDiff line numberDiff line change
@@ -18,4 +18,7 @@ extern const struct nvkm_nvenc_fwif gm107_nvenc_fwif[];
1818

1919
int nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *, struct nvkm_device *, enum nvkm_subdev_type,
2020
int, struct nvkm_nvenc **pnvenc);
21+
22+
int r535_nvenc_new(const struct nvkm_engine_func *, struct nvkm_device *,
23+
enum nvkm_subdev_type, int, struct nvkm_nvenc **);
2124
#endif

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