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Merge branch 'net-dsa-lantiq_gswip-two-fixes-for-net-stable'
Martin Blumenstingl says: ==================== net: dsa: lantiq_gswip: two fixes for -net/-stable While testing the lantiq_gswip driver in OpenWrt at least one board had a non-working Ethernet port connected to an internal 100Mbit/s PHY22F GPHY. The problem which could be observed: - the PHY would detect the link just fine - ethtool stats would see the TX counter rise - the RX counter in ethtool was stuck at zero It turns out that two independent patches are needed to fix this: - first we need to enable the MII data lines also for internal PHYs - second we need to program the GSWIP_MII_CFG registers for all ports except the CPU port These two patches have also been tested by back-porting them on top of Linux 5.4.86 in OpenWrt. Special thanks to Hauke for debugging and brainstorming this on IRC with me! ==================== Link: https://lore.kernel.org/r/20210103012544.3259029-1-martin.blumenstingl@googlemail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2 parents b40f97b + 709a3c9 commit 08ad483

1 file changed

Lines changed: 7 additions & 20 deletions

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drivers/net/dsa/lantiq_gswip.c

Lines changed: 7 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -92,9 +92,7 @@
9292
GSWIP_MDIO_PHY_FDUP_MASK)
9393

9494
/* GSWIP MII Registers */
95-
#define GSWIP_MII_CFG0 0x00
96-
#define GSWIP_MII_CFG1 0x02
97-
#define GSWIP_MII_CFG5 0x04
95+
#define GSWIP_MII_CFGp(p) (0x2 * (p))
9896
#define GSWIP_MII_CFG_EN BIT(14)
9997
#define GSWIP_MII_CFG_LDCLKDIS BIT(12)
10098
#define GSWIP_MII_CFG_MODE_MIIP 0x0
@@ -392,17 +390,9 @@ static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set,
392390
static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
393391
int port)
394392
{
395-
switch (port) {
396-
case 0:
397-
gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG0);
398-
break;
399-
case 1:
400-
gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG1);
401-
break;
402-
case 5:
403-
gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG5);
404-
break;
405-
}
393+
/* There's no MII_CFG register for the CPU port */
394+
if (!dsa_is_cpu_port(priv->ds, port))
395+
gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
406396
}
407397

408398
static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
@@ -822,9 +812,8 @@ static int gswip_setup(struct dsa_switch *ds)
822812
gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
823813

824814
/* Disable the xMII link */
825-
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 0);
826-
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 1);
827-
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 5);
815+
for (i = 0; i < priv->hw_info->max_ports; i++)
816+
gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i);
828817

829818
/* enable special tag insertion on cpu port */
830819
gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
@@ -1541,9 +1530,7 @@ static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port,
15411530
{
15421531
struct gswip_priv *priv = ds->priv;
15431532

1544-
/* Enable the xMII interface only for the external PHY */
1545-
if (interface != PHY_INTERFACE_MODE_INTERNAL)
1546-
gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
1533+
gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
15471534
}
15481535

15491536
static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,

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