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airliedairlied
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Merge tag 'amd-drm-fixes-5.13-2021-05-13' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-5.13-2021-05-13: amdgpu: - Fixes for flexible array conversions - Fix sysfs attribute init - Harvesting fixes - VCN CG/PG fixes for Picasso radeon: - Fixes for flexible array conversions - Fix for flickering on Oland with multiple 4K displays Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210513163228.3963-1-alexander.deucher@amd.com
2 parents 1db7aa2 + 5c1efb5 commit 08f0cfb

17 files changed

Lines changed: 409 additions & 303 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1006,6 +1006,7 @@ struct amdgpu_device {
10061006
struct amdgpu_df df;
10071007

10081008
struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1009+
uint32_t harvest_ip_mask;
10091010
int num_ip_blocks;
10101011
struct mutex mn_lock;
10111012
DECLARE_HASHTABLE(mn_hash, 7);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1683,6 +1683,19 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
16831683
if (!ip_block_version)
16841684
return -EINVAL;
16851685

1686+
switch (ip_block_version->type) {
1687+
case AMD_IP_BLOCK_TYPE_VCN:
1688+
if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1689+
return 0;
1690+
break;
1691+
case AMD_IP_BLOCK_TYPE_JPEG:
1692+
if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
1693+
return 0;
1694+
break;
1695+
default:
1696+
break;
1697+
}
1698+
16861699
DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
16871700
ip_block_version->funcs->name);
16881701

@@ -3111,7 +3124,6 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
31113124
return amdgpu_device_asic_has_dc_support(adev->asic_type);
31123125
}
31133126

3114-
31153127
static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
31163128
{
31173129
struct amdgpu_device *adev =
@@ -3276,6 +3288,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
32763288
adev->vm_manager.vm_pte_funcs = NULL;
32773289
adev->vm_manager.vm_pte_num_scheds = 0;
32783290
adev->gmc.gmc_funcs = NULL;
3291+
adev->harvest_ip_mask = 0x0;
32793292
adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
32803293
bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
32813294

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -373,6 +373,34 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
373373
return -EINVAL;
374374
}
375375

376+
void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
377+
{
378+
struct binary_header *bhdr;
379+
struct harvest_table *harvest_info;
380+
int i;
381+
382+
bhdr = (struct binary_header *)adev->mman.discovery_bin;
383+
harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
384+
le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
385+
386+
for (i = 0; i < 32; i++) {
387+
if (le32_to_cpu(harvest_info->list[i].hw_id) == 0)
388+
break;
389+
390+
switch (le32_to_cpu(harvest_info->list[i].hw_id)) {
391+
case VCN_HWID:
392+
adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
393+
adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
394+
break;
395+
case DMU_HWID:
396+
adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
397+
break;
398+
default:
399+
break;
400+
}
401+
}
402+
}
403+
376404
int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
377405
{
378406
struct binary_header *bhdr;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929

3030
void amdgpu_discovery_fini(struct amdgpu_device *adev);
3131
int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
32+
void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);
3233
int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
3334
int *major, int *minor, int *revision);
3435
int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);

‎drivers/gpu/drm/amd/amdgpu/nv.c‎

Lines changed: 23 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -623,6 +623,16 @@ static const struct amdgpu_ip_block_version nv_common_ip_block =
623623
.funcs = &nv_common_ip_funcs,
624624
};
625625

626+
static bool nv_is_headless_sku(struct pci_dev *pdev)
627+
{
628+
if ((pdev->device == 0x731E &&
629+
(pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
630+
(pdev->device == 0x7340 && pdev->revision == 0xC9) ||
631+
(pdev->device == 0x7360 && pdev->revision == 0xC7))
632+
return true;
633+
return false;
634+
}
635+
626636
static int nv_reg_base_init(struct amdgpu_device *adev)
627637
{
628638
int r;
@@ -635,6 +645,12 @@ static int nv_reg_base_init(struct amdgpu_device *adev)
635645
goto legacy_init;
636646
}
637647

648+
amdgpu_discovery_harvest_ip(adev);
649+
if (nv_is_headless_sku(adev->pdev)) {
650+
adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
651+
adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
652+
}
653+
638654
return 0;
639655
}
640656

@@ -671,16 +687,6 @@ void nv_set_virt_ops(struct amdgpu_device *adev)
671687
adev->virt.ops = &xgpu_nv_virt_ops;
672688
}
673689

674-
static bool nv_is_headless_sku(struct pci_dev *pdev)
675-
{
676-
if ((pdev->device == 0x731E &&
677-
(pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
678-
(pdev->device == 0x7340 && pdev->revision == 0xC9) ||
679-
(pdev->device == 0x7360 && pdev->revision == 0xC7))
680-
return true;
681-
return false;
682-
}
683-
684690
int nv_set_ip_blocks(struct amdgpu_device *adev)
685691
{
686692
int r;
@@ -728,8 +734,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
728734
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
729735
!amdgpu_sriov_vf(adev))
730736
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
731-
if (!nv_is_headless_sku(adev->pdev))
732-
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
737+
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
733738
amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
734739
if (adev->enable_mes)
735740
amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
@@ -752,8 +757,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
752757
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
753758
!amdgpu_sriov_vf(adev))
754759
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
755-
if (!nv_is_headless_sku(adev->pdev))
756-
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
760+
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
757761
if (!amdgpu_sriov_vf(adev))
758762
amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
759763
break;
@@ -777,7 +781,6 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
777781
amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
778782
if (!amdgpu_sriov_vf(adev))
779783
amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
780-
781784
if (adev->enable_mes)
782785
amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
783786
break;
@@ -1149,6 +1152,11 @@ static int nv_common_early_init(void *handle)
11491152
return -EINVAL;
11501153
}
11511154

1155+
if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1156+
adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
1157+
AMD_PG_SUPPORT_VCN_DPG |
1158+
AMD_PG_SUPPORT_JPEG);
1159+
11521160
if (amdgpu_sriov_vf(adev)) {
11531161
amdgpu_virt_init_setting(adev);
11541162
xgpu_nv_mailbox_set_irq_funcs(adev);

‎drivers/gpu/drm/amd/amdgpu/soc15.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1401,7 +1401,8 @@ static int soc15_common_early_init(void *handle)
14011401
AMD_CG_SUPPORT_MC_MGCG |
14021402
AMD_CG_SUPPORT_MC_LS |
14031403
AMD_CG_SUPPORT_SDMA_MGCG |
1404-
AMD_CG_SUPPORT_SDMA_LS;
1404+
AMD_CG_SUPPORT_SDMA_LS |
1405+
AMD_CG_SUPPORT_VCN_MGCG;
14051406

14061407
adev->pg_flags = AMD_PG_SUPPORT_SDMA |
14071408
AMD_PG_SUPPORT_MMHUB |

‎drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1119,10 +1119,10 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
11191119
UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
11201120
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
11211121

1122-
/* put VCPU into reset */
1123-
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1124-
UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1125-
~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1122+
/* stall UMC channel */
1123+
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1124+
UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1125+
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
11261126

11271127
tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
11281128
UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
@@ -1141,6 +1141,11 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
11411141
UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
11421142
~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
11431143

1144+
/* put VCPU into reset */
1145+
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1146+
UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1147+
~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1148+
11441149
WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
11451150

11461151
vcn_v1_0_enable_clock_gating(adev);

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -650,6 +650,7 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct
650650

651651
/* File created at /sys/class/drm/card0/device/hdcp_srm*/
652652
hdcp_work[0].attr = data_attr;
653+
sysfs_bin_attr_init(&hdcp_work[0].attr);
653654

654655
if (sysfs_create_bin_file(&adev->dev->kobj, &hdcp_work[0].attr))
655656
DRM_WARN("Failed to create device file hdcp_srm");

‎drivers/gpu/drm/amd/include/amd_shared.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,12 @@ enum PP_FEATURE_MASK {
216216
PP_GFX_DCS_MASK = 0x80000,
217217
};
218218

219+
enum amd_harvest_ip_mask {
220+
AMD_HARVEST_IP_VCN_MASK = 0x1,
221+
AMD_HARVEST_IP_JPEG_MASK = 0x2,
222+
AMD_HARVEST_IP_DMU_MASK = 0x4,
223+
};
224+
219225
enum DC_FEATURE_MASK {
220226
DC_FBC_MASK = 0x1,
221227
DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,

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