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torvaldstorvalds
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Merge tag 'perf-tools-for-v5.19-2022-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux
Pull more perf tools updates from Arnaldo Carvalho de Melo: - Add BPF based off-CPU profiling - Improvements for system wide recording, specially for Intel PT - Improve DWARF unwinding on arm64 - Support Arm CoreSight trace data disassembly in 'perf script' python - Fix build with new libbpf version, related to supporting older versions of distro released libbpf packages - Fix event syntax error caused by ExtSel in the JSON events infra - Use stdio interface if slang is not supported in 'perf c2c' - Add 'perf test' checking for perf stat CSV output - Sync the msr-index.h copy with the kernel sources * tag 'perf-tools-for-v5.19-2022-05-28' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: (38 commits) tools arch x86: Sync the msr-index.h copy with the kernel sources perf scripts python: Support Arm CoreSight trace data disassembly perf scripting python: Expose dso and map information perf jevents: Fix event syntax error caused by ExtSel perf tools arm64: Add support for VG register perf unwind arm64: Decouple Libunwind register names from Perf perf unwind: Use dynamic register set for DWARF unwind perf tools arm64: Copy perf_regs.h from the kernel perf unwind arm64: Use perf's copy of kernel headers perf c2c: Use stdio interface if slang is not supported perf test: Add a basic offcpu profiling test perf record: Add cgroup support for off-cpu profiling perf record: Handle argument change in sched_switch perf record: Implement basic filtering for off-cpu perf record: Enable off-cpu analysis with BPF perf report: Do not extend sample type of bpf-output event perf test: Add checking for perf stat CSV output. perf tools: Allow system-wide events to keep their own threads perf tools: Allow system-wide events to keep their own CPUs libperf evsel: Add comments for booleans ...
2 parents 664a393 + 9dde6ca commit 09f73a1

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Lines changed: 1594 additions & 197 deletions

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‎tools/arch/arm64/include/uapi/asm/perf_regs.h‎

Lines changed: 6 additions & 1 deletion
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@@ -36,6 +36,11 @@ enum perf_event_arm_regs {
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PERF_REG_ARM64_LR,
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PERF_REG_ARM64_SP,
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PERF_REG_ARM64_PC,
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PERF_REG_ARM64_MAX,
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/* Extended/pseudo registers */
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PERF_REG_ARM64_VG = 46, // SVE Vector Granule
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PERF_REG_ARM64_MAX = PERF_REG_ARM64_PC + 1,
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PERF_REG_ARM64_EXTENDED_MAX = PERF_REG_ARM64_VG + 1
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};
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#endif /* _ASM_ARM64_PERF_REGS_H */

‎tools/arch/x86/include/asm/msr-index.h‎

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@@ -76,6 +76,8 @@
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/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
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#define MSR_IA32_CORE_CAPS 0x000000cf
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#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2
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#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
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#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
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#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
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@@ -154,6 +156,11 @@
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#define MSR_IA32_POWER_CTL 0x000001fc
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#define MSR_IA32_POWER_CTL_BIT_EE 19
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/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
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#define MSR_INTEGRITY_CAPS 0x000002d9
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#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
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#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
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#define MSR_LBR_NHM_FROM 0x00000680
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#define MSR_LBR_NHM_TO 0x000006c0
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#define MSR_LBR_CORE_FROM 0x00000040
@@ -312,6 +319,7 @@
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/* Run Time Average Power Limiting (RAPL) Interface */
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#define MSR_VR_CURRENT_CONFIG 0x00000601
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#define MSR_RAPL_POWER_UNIT 0x00000606
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#define MSR_PKG_POWER_LIMIT 0x00000610
@@ -502,8 +510,10 @@
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#define MSR_AMD64_SEV 0xc0010131
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#define MSR_AMD64_SEV_ENABLED_BIT 0
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#define MSR_AMD64_SEV_ES_ENABLED_BIT 1
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#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2
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#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
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#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
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#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
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#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
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@@ -524,6 +534,11 @@
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#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16)
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#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
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/* AMD Performance Counter Global Status and Control MSRs */
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#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
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#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
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#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
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/* Fam 17h MSRs */
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#define MSR_F17H_IRPERF 0xc00000e9
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@@ -688,6 +703,10 @@
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#define MSR_IA32_PERF_CTL 0x00000199
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#define INTEL_PERF_CTL_MASK 0xffff
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/* AMD Branch Sampling configuration */
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#define MSR_AMD_DBG_EXTN_CFG 0xc000010f
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#define MSR_AMD_SAMP_BR_FROM 0xc0010300
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#define MSR_IA32_MPERF 0x000000e7
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#define MSR_IA32_APERF 0x000000e8
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‎tools/build/Makefile.feature‎

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@@ -99,6 +99,10 @@ FEATURE_TESTS_EXTRA := \
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clang \
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libbpf \
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libbpf-btf__load_from_kernel_by_id \
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libbpf-bpf_prog_load \
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libbpf-bpf_object__next_program \
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libbpf-bpf_object__next_map \
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libbpf-bpf_create_map \
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libpfm4 \
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libdebuginfod \
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clang-bpf-co-re

‎tools/build/feature/Makefile‎

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@@ -58,6 +58,11 @@ FILES= \
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test-bpf.bin \
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test-libbpf.bin \
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test-libbpf-btf__load_from_kernel_by_id.bin \
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test-libbpf-bpf_prog_load.bin \
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test-libbpf-bpf_map_create.bin \
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test-libbpf-bpf_object__next_program.bin \
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test-libbpf-bpf_object__next_map.bin \
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test-libbpf-btf__raw_data.bin \
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test-get_cpuid.bin \
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test-sdt.bin \
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test-cxx.bin \
@@ -291,6 +296,21 @@ $(OUTPUT)test-libbpf.bin:
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$(OUTPUT)test-libbpf-btf__load_from_kernel_by_id.bin:
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$(BUILD) -lbpf
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$(OUTPUT)test-libbpf-bpf_prog_load.bin:
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$(BUILD) -lbpf
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$(OUTPUT)test-libbpf-bpf_map_create.bin:
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$(BUILD) -lbpf
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$(OUTPUT)test-libbpf-bpf_object__next_program.bin:
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$(BUILD) -lbpf
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$(OUTPUT)test-libbpf-bpf_object__next_map.bin:
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$(BUILD) -lbpf
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$(OUTPUT)test-libbpf-btf__raw_data.bin:
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$(BUILD) -lbpf
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$(OUTPUT)test-sdt.bin:
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$(BUILD)
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‎tools/build/feature/test-libbpf-bpf_map_create.c‎

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// SPDX-License-Identifier: GPL-2.0
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#include <bpf/bpf.h>
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int main(void)
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{
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return bpf_map_create(0 /* map_type */, NULL /* map_name */, 0, /* key_size */,
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0 /* value_size */, 0 /* max_entries */, NULL /* opts */);
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}

‎tools/build/feature/test-libbpf-bpf_object__next_map.c‎

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// SPDX-License-Identifier: GPL-2.0
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#include <bpf/libbpf.h>
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int main(void)
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{
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bpf_object__next_map(NULL /* obj */, NULL /* prev */);
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return 0;
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}

‎tools/build/feature/test-libbpf-bpf_object__next_program.c‎

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// SPDX-License-Identifier: GPL-2.0
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#include <bpf/libbpf.h>
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int main(void)
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{
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bpf_object__next_program(NULL /* obj */, NULL /* prev */);
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return 0;
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}

‎tools/build/feature/test-libbpf-bpf_prog_load.c‎

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// SPDX-License-Identifier: GPL-2.0
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#include <bpf/bpf.h>
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int main(void)
5+
{
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return bpf_prog_load(0 /* prog_type */, NULL /* prog_name */,
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NULL /* license */, NULL /* insns */,
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0 /* insn_cnt */, NULL /* opts */);
9+
}

‎tools/build/feature/test-libbpf-btf__load_from_kernel_by_id.c‎

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@@ -1,7 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <bpf/libbpf.h>
2+
#include <bpf/btf.h>
33

44
int main(void)
55
{
6-
return btf__load_from_kernel_by_id(20151128, NULL);
6+
btf__load_from_kernel_by_id(20151128);
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return 0;
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}

‎tools/build/feature/test-libbpf-btf__raw_data.c‎

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// SPDX-License-Identifier: GPL-2.0
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#include <bpf/btf.h>
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int main(void)
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{
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btf__raw_data(NULL /* btf_ro */, NULL /* size */);
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return 0;
8+
}

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