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Paloma Arellanolumag
Paloma Arellano
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lumag
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drm/msm/dpu: move dpu_encoder_helper_phys_setup_cdm to dpu_encoder
Move dpu_encoder_helper_phys_setup_cdm to dpu_encoder in preparation for implementing YUV420 over DP, which requires CDM compatibility. Changes in v2: - Slightly change the wording of the commit text to make clear that YUV over DP requires CDM Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579611/ Link: https://lore.kernel.org/r/20240222194025.25329-6-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
1 parent 7cde7ce commit 0ab07bb

3 files changed

Lines changed: 87 additions & 83 deletions

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‎drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2133,6 +2133,84 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
21332133
ctl->ops.clear_pending_flush(ctl);
21342134
}
21352135

2136+
void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
2137+
const struct dpu_format *dpu_fmt,
2138+
u32 output_type)
2139+
{
2140+
struct dpu_hw_cdm *hw_cdm;
2141+
struct dpu_hw_cdm_cfg *cdm_cfg;
2142+
struct dpu_hw_pingpong *hw_pp;
2143+
int ret;
2144+
2145+
if (!phys_enc)
2146+
return;
2147+
2148+
cdm_cfg = &phys_enc->cdm_cfg;
2149+
hw_pp = phys_enc->hw_pp;
2150+
hw_cdm = phys_enc->hw_cdm;
2151+
2152+
if (!hw_cdm)
2153+
return;
2154+
2155+
if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {
2156+
DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent),
2157+
dpu_fmt->base.pixel_format);
2158+
if (hw_cdm->ops.bind_pingpong_blk)
2159+
hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
2160+
2161+
return;
2162+
}
2163+
2164+
memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));
2165+
2166+
cdm_cfg->output_width = phys_enc->cached_mode.hdisplay;
2167+
cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
2168+
cdm_cfg->output_fmt = dpu_fmt;
2169+
cdm_cfg->output_type = output_type;
2170+
cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?
2171+
CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
2172+
cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
2173+
2174+
/* enable 10 bit logic */
2175+
switch (cdm_cfg->output_fmt->chroma_sample) {
2176+
case DPU_CHROMA_RGB:
2177+
cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
2178+
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2179+
break;
2180+
case DPU_CHROMA_H2V1:
2181+
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
2182+
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2183+
break;
2184+
case DPU_CHROMA_420:
2185+
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
2186+
cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
2187+
break;
2188+
case DPU_CHROMA_H1V2:
2189+
default:
2190+
DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
2191+
DRMID(phys_enc->parent));
2192+
cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
2193+
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2194+
break;
2195+
}
2196+
2197+
DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
2198+
DRMID(phys_enc->parent), cdm_cfg->output_width,
2199+
cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format,
2200+
cdm_cfg->output_type, cdm_cfg->output_bit_depth,
2201+
cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
2202+
2203+
if (hw_cdm->ops.enable) {
2204+
cdm_cfg->pp_id = hw_pp->idx;
2205+
ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
2206+
if (ret < 0) {
2207+
DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n",
2208+
DRMID(phys_enc->parent), ret);
2209+
return;
2210+
}
2211+
}
2212+
}
2213+
21362214
#ifdef CONFIG_DEBUG_FS
21372215
static int _dpu_encoder_status_show(struct seq_file *s, void *data)
21382216
{

‎drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -374,6 +374,15 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
374374
*/
375375
void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
376376

377+
/**
378+
* dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block
379+
* @phys_enc: Pointer to physical encoder
380+
* @output_type: HDMI/WB
381+
*/
382+
void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
383+
const struct dpu_format *dpu_fmt,
384+
u32 output_type);
385+
377386
/**
378387
* dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception
379388
* @drm_enc: Pointer to drm encoder structure

‎drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c‎

Lines changed: 0 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -264,89 +264,6 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
264264
}
265265
}
266266

267-
/**
268-
* dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block
269-
* This API does not handle DPU_CHROMA_H1V2.
270-
* @phys_enc:Pointer to physical encoder
271-
*/
272-
static void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
273-
const struct dpu_format *dpu_fmt,
274-
u32 output_type)
275-
{
276-
struct dpu_hw_cdm *hw_cdm;
277-
struct dpu_hw_cdm_cfg *cdm_cfg;
278-
struct dpu_hw_pingpong *hw_pp;
279-
int ret;
280-
281-
if (!phys_enc)
282-
return;
283-
284-
cdm_cfg = &phys_enc->cdm_cfg;
285-
hw_pp = phys_enc->hw_pp;
286-
hw_cdm = phys_enc->hw_cdm;
287-
288-
if (!hw_cdm)
289-
return;
290-
291-
if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {
292-
DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent),
293-
dpu_fmt->base.pixel_format);
294-
if (hw_cdm->ops.bind_pingpong_blk)
295-
hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
296-
297-
return;
298-
}
299-
300-
memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));
301-
302-
cdm_cfg->output_width = phys_enc->cached_mode.hdisplay;
303-
cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
304-
cdm_cfg->output_fmt = dpu_fmt;
305-
cdm_cfg->output_type = output_type;
306-
cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?
307-
CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
308-
cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
309-
310-
/* enable 10 bit logic */
311-
switch (cdm_cfg->output_fmt->chroma_sample) {
312-
case DPU_CHROMA_RGB:
313-
cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
314-
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
315-
break;
316-
case DPU_CHROMA_H2V1:
317-
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
318-
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
319-
break;
320-
case DPU_CHROMA_420:
321-
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
322-
cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
323-
break;
324-
case DPU_CHROMA_H1V2:
325-
default:
326-
DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
327-
DRMID(phys_enc->parent));
328-
cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
329-
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
330-
break;
331-
}
332-
333-
DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
334-
DRMID(phys_enc->parent), cdm_cfg->output_width,
335-
cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format,
336-
cdm_cfg->output_type, cdm_cfg->output_bit_depth,
337-
cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
338-
339-
if (hw_cdm->ops.enable) {
340-
cdm_cfg->pp_id = hw_pp->idx;
341-
ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
342-
if (ret < 0) {
343-
DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n",
344-
DRMID(phys_enc->parent), ret);
345-
return;
346-
}
347-
}
348-
}
349-
350267
/**
351268
* _dpu_encoder_phys_wb_update_flush - flush hardware update
352269
* @phys_enc: Pointer to physical encoder

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