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pmalgujar-mrvlAndi Shyti
pmalgujar-mrvl
authored and
Andi Shyti
committed
i2c: octeon: Add platform prefix to macros
The macros for TWSI register's offset are generically named, rename them to be platform specific macros by adding 'OCTEON_REG' as prefix. Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
1 parent 03240f8 commit 0b042c7

2 files changed

Lines changed: 31 additions & 31 deletions

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‎drivers/i2c/busses/i2c-octeon-core.c‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c)
8585

8686
static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)
8787
{
88-
return (__raw_readq(i2c->twsi_base + SW_TWSI(i2c)) & SW_TWSI_V) == 0;
88+
return (__raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)) & SW_TWSI_V) == 0;
8989
}
9090

9191
static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
@@ -185,10 +185,10 @@ static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
185185

186186
/*
187187
* This is ugly... in HLC mode the status is not in the status register
188-
* but in the lower 8 bits of SW_TWSI.
188+
* but in the lower 8 bits of OCTEON_REG_SW_TWSI.
189189
*/
190190
if (i2c->hlc_enabled)
191-
stat = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
191+
stat = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
192192
else
193193
stat = octeon_i2c_stat_read(i2c);
194194

@@ -424,20 +424,20 @@ static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
424424
else
425425
cmd |= SW_TWSI_OP_7;
426426

427-
octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
427+
octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
428428
ret = octeon_i2c_hlc_wait(i2c);
429429
if (ret)
430430
goto err;
431431

432-
cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
432+
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
433433
if ((cmd & SW_TWSI_R) == 0)
434434
return octeon_i2c_check_status(i2c, false);
435435

436436
for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
437437
msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
438438

439439
if (msgs[0].len > 4) {
440-
cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
440+
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));
441441
for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
442442
msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
443443
}
@@ -474,15 +474,15 @@ static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
474474

475475
for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
476476
ext |= (u64)msgs[0].buf[j] << (8 * i);
477-
octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
477+
octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));
478478
}
479479

480-
octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
480+
octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
481481
ret = octeon_i2c_hlc_wait(i2c);
482482
if (ret)
483483
goto err;
484484

485-
cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
485+
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
486486
if ((cmd & SW_TWSI_R) == 0)
487487
return octeon_i2c_check_status(i2c, false);
488488

@@ -515,27 +515,27 @@ static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs
515515
cmd |= SW_TWSI_EIA;
516516
ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
517517
cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
518-
octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
518+
octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));
519519
} else {
520520
cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
521521
}
522522

523523
octeon_i2c_hlc_int_clear(i2c);
524-
octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
524+
octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
525525

526526
ret = octeon_i2c_hlc_wait(i2c);
527527
if (ret)
528528
goto err;
529529

530-
cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
530+
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
531531
if ((cmd & SW_TWSI_R) == 0)
532532
return octeon_i2c_check_status(i2c, false);
533533

534534
for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
535535
msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
536536

537537
if (msgs[1].len > 4) {
538-
cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT(i2c));
538+
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));
539539
for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
540540
msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
541541
}
@@ -582,16 +582,16 @@ static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msg
582582
set_ext = true;
583583
}
584584
if (set_ext)
585-
octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c));
585+
octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));
586586

587587
octeon_i2c_hlc_int_clear(i2c);
588-
octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c));
588+
octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
589589

590590
ret = octeon_i2c_hlc_wait(i2c);
591591
if (ret)
592592
goto err;
593593

594-
cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
594+
cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
595595
if ((cmd & SW_TWSI_R) == 0)
596596
return octeon_i2c_check_status(i2c, false);
597597

@@ -737,13 +737,13 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c)
737737
if (is_plat_otx2) {
738738
u64 mode;
739739

740-
mode = __raw_readq(i2c->twsi_base + MODE(i2c));
740+
mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));
741741
/* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */
742742
if (!IS_LS_FREQ(i2c->twsi_freq))
743743
mode |= TWSX_MODE_HS_MASK;
744744
else
745745
mode &= ~TWSX_MODE_HS_MASK;
746-
octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c));
746+
octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c));
747747
}
748748
}
749749

‎drivers/i2c/busses/i2c-octeon-core.h‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -97,10 +97,10 @@ struct octeon_i2c_reg_offset {
9797
unsigned int mode;
9898
};
9999

100-
#define SW_TWSI(x) (x->roff.sw_twsi)
101-
#define TWSI_INT(x) (x->roff.twsi_int)
102-
#define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext)
103-
#define MODE(x) ((x)->roff.mode)
100+
#define OCTEON_REG_SW_TWSI(x) ((x)->roff.sw_twsi)
101+
#define OCTEON_REG_TWSI_INT(x) ((x)->roff.twsi_int)
102+
#define OCTEON_REG_SW_TWSI_EXT(x) ((x)->roff.sw_twsi_ext)
103+
#define OCTEON_REG_MODE(x) ((x)->roff.mode)
104104

105105
/* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */
106106
#define TWSX_MODE_REFCLK_SRC BIT(4)
@@ -143,16 +143,16 @@ static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
143143
* @eop_reg: Register selector
144144
* @data: Value to be written
145145
*
146-
* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
146+
* The I2C core registers are accessed indirectly via the OCTEON_REG_SW_TWSI CSR.
147147
*/
148148
static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
149149
{
150150
int tries = 1000;
151151
u64 tmp;
152152

153-
__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c));
153+
__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
154154
do {
155-
tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
155+
tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
156156
if (--tries < 0)
157157
return;
158158
} while ((tmp & SW_TWSI_V) != 0);
@@ -178,9 +178,9 @@ static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg,
178178
int tries = 1000;
179179
u64 tmp;
180180

181-
__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c));
181+
__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
182182
do {
183-
tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
183+
tmp = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));
184184
if (--tries < 0) {
185185
/* signal that the returned data is invalid */
186186
if (error)
@@ -200,24 +200,24 @@ static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg,
200200
octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL)
201201

202202
/**
203-
* octeon_i2c_read_int - read the TWSI_INT register
203+
* octeon_i2c_read_int - read the OCTEON_REG_TWSI_INT register
204204
* @i2c: The struct octeon_i2c
205205
*
206206
* Returns the value of the register.
207207
*/
208208
static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
209209
{
210-
return __raw_readq(i2c->twsi_base + TWSI_INT(i2c));
210+
return __raw_readq(i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));
211211
}
212212

213213
/**
214-
* octeon_i2c_write_int - write the TWSI_INT register
214+
* octeon_i2c_write_int - write the OCTEON_REG_TWSI_INT register
215215
* @i2c: The struct octeon_i2c
216216
* @data: Value to be written
217217
*/
218218
static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
219219
{
220-
octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c));
220+
octeon_i2c_writeq_flush(data, i2c->twsi_base + OCTEON_REG_TWSI_INT(i2c));
221221
}
222222

223223
#define IS_LS_FREQ(twsi_freq) ((twsi_freq) <= 400000)

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