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alexelderdlan17
alexelder
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dlan17
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riscv: dts: spacemit: PCIe and PHY-related updates
Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 board. The combo PHY is used for USB on this board, and that will be enabled when USB 3 support is accepted. The combo PHY must perform a calibration step to determine configuration values used by the PCIe-only PHYs. As a result, it must be enabled if either of the other two PHYs is enabled. Signed-off-by: Alex Elder <elder@riscstar.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Tested-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251218151235.454997-6-elder@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
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‎arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts‎

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Original file line numberDiff line numberDiff line change
@@ -61,6 +61,12 @@
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};
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};
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&combo_phy {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_3_cfg>;
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status = "okay";
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};
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&emmc {
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bus-width = <8>;
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mmc-hs400-1_8v;
@@ -272,6 +278,36 @@
272278
};
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};
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&pcie1_phy {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_3_cfg>;
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status = "okay";
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};
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&pcie1_port {
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phys = <&pcie1_phy>;
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};
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&pcie1 {
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vpcie3v3-supply = <&pcie_vcc_3v3>;
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status = "okay";
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};
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&pcie2_phy {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2_4_cfg>;
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status = "okay";
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};
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&pcie2_port {
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phys = <&pcie2_phy>;
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};
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&pcie2 {
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vpcie3v3-supply = <&pcie_vcc_3v3>;
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status = "okay";
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};
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275311
&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_2_cfg>;

‎arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -530,6 +530,39 @@
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};
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};
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pcie0_3_cfg: pcie0-3-cfg {
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pcie0-3-pins {
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pinmux = <K1_PADCONF(54, 3)>, /* PERST# */
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<K1_PADCONF(55, 3)>, /* WAKE# */
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<K1_PADCONF(53, 3)>; /* CLKREQ# */
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539+
bias-pull-up = <0>;
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drive-strength = <21>;
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};
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};
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pcie1_3_cfg: pcie1-3-cfg {
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pcie1-3-pins {
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pinmux = <K1_PADCONF(59, 4)>, /* PERST# */
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<K1_PADCONF(60, 4)>, /* WAKE# */
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<K1_PADCONF(61, 4)>; /* CLKREQ# */
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bias-pull-up = <0>;
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drive-strength = <21>;
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};
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};
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pcie2_4_cfg: pcie2-4-cfg {
556+
pcie2-4-pins {
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pinmux = <K1_PADCONF(62, 4)>, /* PERST# */
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<K1_PADCONF(112, 3)>, /* WAKE# */
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<K1_PADCONF(117, 4)>; /* CLKREQ# */
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bias-pull-up = <0>;
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drive-strength = <21>;
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};
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};
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533566
pwm14_1_cfg: pwm14-1-cfg {
534567
pwm14-1-pins {
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pinmux = <K1_PADCONF(44, 4)>;

‎arch/riscv/boot/dts/spacemit/k1.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
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*/
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66
#include <dt-bindings/clock/spacemit,k1-syscon.h>
7+
#include <dt-bindings/phy/phy.h>
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/dts-v1/;
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/ {
@@ -423,6 +424,52 @@
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status = "disabled";
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};
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combo_phy: phy@c0b10000 {
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compatible = "spacemit,k1-combo-phy";
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reg = <0x0 0xc0b10000 0x0 0x1000>;
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clocks = <&vctcxo_24m>,
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<&syscon_apmu CLK_PCIE0_DBI>,
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<&syscon_apmu CLK_PCIE0_MASTER>,
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<&syscon_apmu CLK_PCIE0_SLAVE>;
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clock-names = "refclk",
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"dbi",
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"mstr",
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"slv";
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resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
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<&syscon_apmu RESET_PCIE0_DBI>,
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<&syscon_apmu RESET_PCIE0_MASTER>,
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<&syscon_apmu RESET_PCIE0_SLAVE>;
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reset-names = "phy",
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"dbi",
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"mstr",
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"slv";
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#phy-cells = <1>;
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spacemit,apmu = <&syscon_apmu>;
448+
status = "disabled";
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};
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451+
pcie1_phy: phy@c0c10000 {
452+
compatible = "spacemit,k1-pcie-phy";
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reg = <0x0 0xc0c10000 0x0 0x1000>;
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clocks = <&vctcxo_24m>;
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clock-names = "refclk";
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resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
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reset-names = "phy";
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#phy-cells = <0>;
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status = "disabled";
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};
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pcie2_phy: phy@c0d10000 {
463+
compatible = "spacemit,k1-pcie-phy";
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reg = <0x0 0xc0d10000 0x0 0x1000>;
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clocks = <&vctcxo_24m>;
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clock-names = "refclk";
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resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
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reset-names = "phy";
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#phy-cells = <0>;
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status = "disabled";
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};
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426473
syscon_apbc: system-controller@d4015000 {
427474
compatible = "spacemit,k1-syscon-apbc";
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reg = <0x0 0xd4015000 0x0 0x1000>;
@@ -969,6 +1016,135 @@
9691016
#size-cells = <2>;
9701017
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
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<0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
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pcie0: pcie@ca000000 {
1020+
device_type = "pci";
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compatible = "spacemit,k1-pcie";
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reg = <0x0 0xca000000 0x0 0x00001000>,
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<0x0 0xca300000 0x0 0x0001ff24>,
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<0x0 0x8f000000 0x0 0x00002000>,
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<0x0 0xc0b20000 0x0 0x00001000>;
1026+
reg-names = "dbi",
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"atu",
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"config",
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"link";
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#address-cells = <3>;
1031+
#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>,
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<0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>;
1034+
interrupts = <141>;
1035+
interrupt-names = "msi";
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clocks = <&syscon_apmu CLK_PCIE0_DBI>,
1037+
<&syscon_apmu CLK_PCIE0_MASTER>,
1038+
<&syscon_apmu CLK_PCIE0_SLAVE>;
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clock-names = "dbi",
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"mstr",
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"slv";
1042+
resets = <&syscon_apmu RESET_PCIE0_DBI>,
1043+
<&syscon_apmu RESET_PCIE0_MASTER>,
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<&syscon_apmu RESET_PCIE0_SLAVE>;
1045+
reset-names = "dbi",
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"mstr",
1047+
"slv";
1048+
spacemit,apmu = <&syscon_apmu 0x03cc>;
1049+
status = "disabled";
1050+
1051+
pcie0_port: pcie@0 {
1052+
device_type = "pci";
1053+
compatible = "pciclass,0604";
1054+
reg = <0x0 0x0 0x0 0x0 0x0>;
1055+
bus-range = <0x01 0xff>;
1056+
#address-cells = <3>;
1057+
#size-cells = <2>;
1058+
ranges;
1059+
};
1060+
};
1061+
1062+
pcie1: pcie@ca400000 {
1063+
device_type = "pci";
1064+
compatible = "spacemit,k1-pcie";
1065+
reg = <0x0 0xca400000 0x0 0x00001000>,
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<0x0 0xca700000 0x0 0x0001ff24>,
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<0x0 0x9f000000 0x0 0x00002000>,
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<0x0 0xc0c20000 0x0 0x00001000>;
1069+
reg-names = "dbi",
1070+
"atu",
1071+
"config",
1072+
"link";
1073+
#address-cells = <3>;
1074+
#size-cells = <2>;
1075+
ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>,
1076+
<0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>;
1077+
interrupts = <142>;
1078+
interrupt-names = "msi";
1079+
clocks = <&syscon_apmu CLK_PCIE1_DBI>,
1080+
<&syscon_apmu CLK_PCIE1_MASTER>,
1081+
<&syscon_apmu CLK_PCIE1_SLAVE>;
1082+
clock-names = "dbi",
1083+
"mstr",
1084+
"slv";
1085+
resets = <&syscon_apmu RESET_PCIE1_DBI>,
1086+
<&syscon_apmu RESET_PCIE1_MASTER>,
1087+
<&syscon_apmu RESET_PCIE1_SLAVE>;
1088+
reset-names = "dbi",
1089+
"mstr",
1090+
"slv";
1091+
spacemit,apmu = <&syscon_apmu 0x3d4>;
1092+
status = "disabled";
1093+
1094+
pcie1_port: pcie@0 {
1095+
device_type = "pci";
1096+
compatible = "pciclass,0604";
1097+
reg = <0x0 0x0 0x0 0x0 0x0>;
1098+
bus-range = <0x01 0xff>;
1099+
#address-cells = <3>;
1100+
#size-cells = <2>;
1101+
ranges;
1102+
};
1103+
};
1104+
1105+
pcie2: pcie@ca800000 {
1106+
device_type = "pci";
1107+
compatible = "spacemit,k1-pcie";
1108+
reg = <0x0 0xca800000 0x0 0x00001000>,
1109+
<0x0 0xcab00000 0x0 0x0001ff24>,
1110+
<0x0 0xb7000000 0x0 0x00002000>,
1111+
<0x0 0xc0d20000 0x0 0x00001000>;
1112+
reg-names = "dbi",
1113+
"atu",
1114+
"config",
1115+
"link";
1116+
#address-cells = <3>;
1117+
#size-cells = <2>;
1118+
ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>,
1119+
<0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>,
1120+
<0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>;
1121+
interrupts = <143>;
1122+
interrupt-names = "msi";
1123+
clocks = <&syscon_apmu CLK_PCIE2_DBI>,
1124+
<&syscon_apmu CLK_PCIE2_MASTER>,
1125+
<&syscon_apmu CLK_PCIE2_SLAVE>;
1126+
clock-names = "dbi",
1127+
"mstr",
1128+
"slv";
1129+
resets = <&syscon_apmu RESET_PCIE2_DBI>,
1130+
<&syscon_apmu RESET_PCIE2_MASTER>,
1131+
<&syscon_apmu RESET_PCIE2_SLAVE>;
1132+
reset-names = "dbi",
1133+
"mstr",
1134+
"slv";
1135+
spacemit,apmu = <&syscon_apmu 0x3dc>;
1136+
status = "disabled";
1137+
1138+
pcie2_port: pcie@0 {
1139+
device_type = "pci";
1140+
compatible = "pciclass,0604";
1141+
reg = <0x0 0x0 0x0 0x0 0x0>;
1142+
bus-range = <0x01 0xff>;
1143+
#address-cells = <3>;
1144+
#size-cells = <2>;
1145+
ranges;
1146+
};
1147+
};
9721148
};
9731149

9741150
storage-bus {

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