@@ -481,150 +481,40 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
481481 MT8183_MEMIF_BASE (HDMI , -1 , -1 , -1 ),
482482};
483483
484+ #define MT8183_AFE_IRQ_BASE (_id , _fs_reg , _fs_shift , _fs_maskbit ) \
485+ [MT8183_IRQ_##_id] = { \
486+ .id = MT8183_IRQ_##_id, \
487+ .irq_cnt_reg = AFE_IRQ_MCU_CNT##_id, \
488+ .irq_cnt_shift = 0, \
489+ .irq_cnt_maskbit = 0x3ffff, \
490+ .irq_fs_reg = _fs_reg, \
491+ .irq_fs_shift = _fs_shift, \
492+ .irq_fs_maskbit = _fs_maskbit, \
493+ .irq_en_reg = AFE_IRQ_MCU_CON0, \
494+ .irq_en_shift = IRQ##_id##_MCU_ON_SFT, \
495+ .irq_clr_reg = AFE_IRQ_MCU_CLR, \
496+ .irq_clr_shift = IRQ##_id##_MCU_CLR_SFT, \
497+ }
498+
499+ #define MT8183_AFE_IRQ (_id ) \
500+ MT8183_AFE_IRQ_BASE(_id, AFE_IRQ_MCU_CON1 + _id / 8 * 4, \
501+ IRQ##_id##_MCU_MODE_SFT, \
502+ IRQ##_id##_MCU_MODE_MASK)
503+
504+ #define MT8183_AFE_IRQ_NOFS (_id ) MT8183_AFE_IRQ_BASE(_id, -1, -1, -1)
505+
484506static const struct mtk_base_irq_data irq_data [MT8183_IRQ_NUM ] = {
485- [MT8183_IRQ_0 ] = {
486- .id = MT8183_IRQ_0 ,
487- .irq_cnt_reg = AFE_IRQ_MCU_CNT0 ,
488- .irq_cnt_shift = 0 ,
489- .irq_cnt_maskbit = 0x3ffff ,
490- .irq_fs_reg = AFE_IRQ_MCU_CON1 ,
491- .irq_fs_shift = IRQ0_MCU_MODE_SFT ,
492- .irq_fs_maskbit = IRQ0_MCU_MODE_MASK ,
493- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
494- .irq_en_shift = IRQ0_MCU_ON_SFT ,
495- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
496- .irq_clr_shift = IRQ0_MCU_CLR_SFT ,
497- },
498- [MT8183_IRQ_1 ] = {
499- .id = MT8183_IRQ_1 ,
500- .irq_cnt_reg = AFE_IRQ_MCU_CNT1 ,
501- .irq_cnt_shift = 0 ,
502- .irq_cnt_maskbit = 0x3ffff ,
503- .irq_fs_reg = AFE_IRQ_MCU_CON1 ,
504- .irq_fs_shift = IRQ1_MCU_MODE_SFT ,
505- .irq_fs_maskbit = IRQ1_MCU_MODE_MASK ,
506- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
507- .irq_en_shift = IRQ1_MCU_ON_SFT ,
508- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
509- .irq_clr_shift = IRQ1_MCU_CLR_SFT ,
510- },
511- [MT8183_IRQ_2 ] = {
512- .id = MT8183_IRQ_2 ,
513- .irq_cnt_reg = AFE_IRQ_MCU_CNT2 ,
514- .irq_cnt_shift = 0 ,
515- .irq_cnt_maskbit = 0x3ffff ,
516- .irq_fs_reg = AFE_IRQ_MCU_CON1 ,
517- .irq_fs_shift = IRQ2_MCU_MODE_SFT ,
518- .irq_fs_maskbit = IRQ2_MCU_MODE_MASK ,
519- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
520- .irq_en_shift = IRQ2_MCU_ON_SFT ,
521- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
522- .irq_clr_shift = IRQ2_MCU_CLR_SFT ,
523- },
524- [MT8183_IRQ_3 ] = {
525- .id = MT8183_IRQ_3 ,
526- .irq_cnt_reg = AFE_IRQ_MCU_CNT3 ,
527- .irq_cnt_shift = 0 ,
528- .irq_cnt_maskbit = 0x3ffff ,
529- .irq_fs_reg = AFE_IRQ_MCU_CON1 ,
530- .irq_fs_shift = IRQ3_MCU_MODE_SFT ,
531- .irq_fs_maskbit = IRQ3_MCU_MODE_MASK ,
532- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
533- .irq_en_shift = IRQ3_MCU_ON_SFT ,
534- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
535- .irq_clr_shift = IRQ3_MCU_CLR_SFT ,
536- },
537- [MT8183_IRQ_4 ] = {
538- .id = MT8183_IRQ_4 ,
539- .irq_cnt_reg = AFE_IRQ_MCU_CNT4 ,
540- .irq_cnt_shift = 0 ,
541- .irq_cnt_maskbit = 0x3ffff ,
542- .irq_fs_reg = AFE_IRQ_MCU_CON1 ,
543- .irq_fs_shift = IRQ4_MCU_MODE_SFT ,
544- .irq_fs_maskbit = IRQ4_MCU_MODE_MASK ,
545- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
546- .irq_en_shift = IRQ4_MCU_ON_SFT ,
547- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
548- .irq_clr_shift = IRQ4_MCU_CLR_SFT ,
549- },
550- [MT8183_IRQ_5 ] = {
551- .id = MT8183_IRQ_5 ,
552- .irq_cnt_reg = AFE_IRQ_MCU_CNT5 ,
553- .irq_cnt_shift = 0 ,
554- .irq_cnt_maskbit = 0x3ffff ,
555- .irq_fs_reg = AFE_IRQ_MCU_CON1 ,
556- .irq_fs_shift = IRQ5_MCU_MODE_SFT ,
557- .irq_fs_maskbit = IRQ5_MCU_MODE_MASK ,
558- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
559- .irq_en_shift = IRQ5_MCU_ON_SFT ,
560- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
561- .irq_clr_shift = IRQ5_MCU_CLR_SFT ,
562- },
563- [MT8183_IRQ_6 ] = {
564- .id = MT8183_IRQ_6 ,
565- .irq_cnt_reg = AFE_IRQ_MCU_CNT6 ,
566- .irq_cnt_shift = 0 ,
567- .irq_cnt_maskbit = 0x3ffff ,
568- .irq_fs_reg = AFE_IRQ_MCU_CON1 ,
569- .irq_fs_shift = IRQ6_MCU_MODE_SFT ,
570- .irq_fs_maskbit = IRQ6_MCU_MODE_MASK ,
571- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
572- .irq_en_shift = IRQ6_MCU_ON_SFT ,
573- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
574- .irq_clr_shift = IRQ6_MCU_CLR_SFT ,
575- },
576- [MT8183_IRQ_7 ] = {
577- .id = MT8183_IRQ_7 ,
578- .irq_cnt_reg = AFE_IRQ_MCU_CNT7 ,
579- .irq_cnt_shift = 0 ,
580- .irq_cnt_maskbit = 0x3ffff ,
581- .irq_fs_reg = AFE_IRQ_MCU_CON1 ,
582- .irq_fs_shift = IRQ7_MCU_MODE_SFT ,
583- .irq_fs_maskbit = IRQ7_MCU_MODE_MASK ,
584- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
585- .irq_en_shift = IRQ7_MCU_ON_SFT ,
586- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
587- .irq_clr_shift = IRQ7_MCU_CLR_SFT ,
588- },
589- [MT8183_IRQ_8 ] = {
590- .id = MT8183_IRQ_8 ,
591- .irq_cnt_reg = AFE_IRQ_MCU_CNT8 ,
592- .irq_cnt_shift = 0 ,
593- .irq_cnt_maskbit = 0x3ffff ,
594- .irq_fs_reg = -1 ,
595- .irq_fs_shift = -1 ,
596- .irq_fs_maskbit = -1 ,
597- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
598- .irq_en_shift = IRQ8_MCU_ON_SFT ,
599- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
600- .irq_clr_shift = IRQ8_MCU_CLR_SFT ,
601- },
602- [MT8183_IRQ_11 ] = {
603- .id = MT8183_IRQ_11 ,
604- .irq_cnt_reg = AFE_IRQ_MCU_CNT11 ,
605- .irq_cnt_shift = 0 ,
606- .irq_cnt_maskbit = 0x3ffff ,
607- .irq_fs_reg = AFE_IRQ_MCU_CON2 ,
608- .irq_fs_shift = IRQ11_MCU_MODE_SFT ,
609- .irq_fs_maskbit = IRQ11_MCU_MODE_MASK ,
610- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
611- .irq_en_shift = IRQ11_MCU_ON_SFT ,
612- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
613- .irq_clr_shift = IRQ11_MCU_CLR_SFT ,
614- },
615- [MT8183_IRQ_12 ] = {
616- .id = MT8183_IRQ_12 ,
617- .irq_cnt_reg = AFE_IRQ_MCU_CNT12 ,
618- .irq_cnt_shift = 0 ,
619- .irq_cnt_maskbit = 0x3ffff ,
620- .irq_fs_reg = AFE_IRQ_MCU_CON2 ,
621- .irq_fs_shift = IRQ12_MCU_MODE_SFT ,
622- .irq_fs_maskbit = IRQ12_MCU_MODE_MASK ,
623- .irq_en_reg = AFE_IRQ_MCU_CON0 ,
624- .irq_en_shift = IRQ12_MCU_ON_SFT ,
625- .irq_clr_reg = AFE_IRQ_MCU_CLR ,
626- .irq_clr_shift = IRQ12_MCU_CLR_SFT ,
627- },
507+ MT8183_AFE_IRQ (0 ),
508+ MT8183_AFE_IRQ (1 ),
509+ MT8183_AFE_IRQ (2 ),
510+ MT8183_AFE_IRQ (3 ),
511+ MT8183_AFE_IRQ (4 ),
512+ MT8183_AFE_IRQ (5 ),
513+ MT8183_AFE_IRQ (6 ),
514+ MT8183_AFE_IRQ (7 ),
515+ MT8183_AFE_IRQ_NOFS (8 ),
516+ MT8183_AFE_IRQ (11 ),
517+ MT8183_AFE_IRQ (12 ),
628518};
629519
630520static bool mt8183_is_volatile_reg (struct device * dev , unsigned int reg )
0 commit comments