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Merge tag 'for-linus' of git://github.com/openrisc/linux
Pull OpenRISC updates from Stafford Horne: - New drivers and OpenRISC support for the LiteX platform - A bug fix to support userspace gdb debugging - Fixes one compile issue with blk-iocost * tag 'for-linus' of git://github.com/openrisc/linux: openrisc: add local64.h to fix blk-iocost build openrisc: fix trap for debugger breakpoint signalling openrisc: add support for LiteX drivers/tty/serial: add LiteUART driver dt-bindings: serial: document LiteUART bindings drivers/soc/litex: add LiteX SoC Controller driver dt-bindings: soc: document LiteX SoC Controller bindings dt-bindings: vendor: add vendor prefix for LiteX
2 parents 8a5be36 + d8398bf commit 0c6c887

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‎Documentation/devicetree/bindings/serial/litex,liteuart.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/serial/litex,liteuart.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: LiteUART serial controller
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maintainers:
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- Karol Gugala <kgugala@antmicro.com>
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- Mateusz Holenko <mholenko@antmicro.com>
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description: |
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LiteUART serial controller is a part of the LiteX FPGA SoC builder. It supports
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multiple CPU architectures, currently including e.g. OpenRISC and RISC-V.
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properties:
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compatible:
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const: litex,liteuart
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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examples:
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- |
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uart0: serial@e0001800 {
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compatible = "litex,liteuart";
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reg = <0xe0001800 0x100>;
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interrupts = <2>;
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};

‎Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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# Copyright 2020 Antmicro <www.antmicro.com>
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: LiteX SoC Controller driver
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description: |
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This is the SoC Controller driver for the LiteX SoC Builder.
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Its purpose is to verify LiteX CSR (Control&Status Register) access
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operations and provide functions for other drivers to read/write CSRs
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and to check if those accessors are ready to be used.
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maintainers:
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- Karol Gugala <kgugala@antmicro.com>
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- Mateusz Holenko <mholenko@antmicro.com>
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properties:
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compatible:
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const: litex,soc-controller
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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examples:
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- |
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soc_ctrl0: soc-controller@f0000000 {
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compatible = "litex,soc-controller";
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reg = <0xf0000000 0xc>;
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status = "okay";
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};
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...

‎Documentation/devicetree/bindings/vendor-prefixes.yaml‎

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description: Linux-specific binding
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"^linx,.*":
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description: Linx Technologies
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"^litex,.*":
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description: LiteX SoC builder
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"^lltc,.*":
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description: Linear Technology Corporation
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"^logicpd,.*":

‎MAINTAINERS‎

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S: Maintained
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F: lib/list-test.c
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LITEX PLATFORM
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M: Karol Gugala <kgugala@antmicro.com>
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M: Mateusz Holenko <mholenko@antmicro.com>
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S: Maintained
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F: Documentation/devicetree/bindings/*/litex,*.yaml
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F: arch/openrisc/boot/dts/or1klitex.dts
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F: drivers/soc/litex/litex_soc_ctrl.c
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F: drivers/tty/serial/liteuart.c
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F: include/linux/litex.h
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LIVE PATCHING
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M: Josh Poimboeuf <jpoimboe@redhat.com>
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M: Jiri Kosina <jikos@kernel.org>

‎arch/openrisc/boot/dts/or1klitex.dts‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* LiteX-based System on Chip
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*
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* Copyright (C) 2019 Antmicro <www.antmicro.com>
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*/
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/dts-v1/;
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/ {
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compatible = "opencores,or1ksim";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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aliases {
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serial0 = &serial0;
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};
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chosen {
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bootargs = "console=liteuart";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <0>;
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clock-frequency = <100000000>;
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};
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};
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pic: pic {
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compatible = "opencores,or1k-pic";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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serial0: serial@e0002000 {
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device_type = "serial";
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compatible = "litex,liteuart";
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reg = <0xe0002000 0x100>;
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};
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soc_ctrl0: soc_controller@e0000000 {
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compatible = "litex,soc-controller";
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reg = <0xe0000000 0xc>;
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status = "okay";
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};
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};

‎arch/openrisc/configs/or1klitex_defconfig‎

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CONFIG_BLK_DEV_INITRD=y
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CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
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CONFIG_BUG_ON_DATA_CORRUPTION=y
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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CONFIG_EMBEDDED=y
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CONFIG_HZ_100=y
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CONFIG_INITRAMFS_SOURCE="openrisc-rootfs.cpio.gz"
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CONFIG_OF_OVERLAY=y
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CONFIG_OPENRISC_BUILTIN_DTB="or1klitex"
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CONFIG_PANIC_ON_OOPS=y
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CONFIG_PRINTK_TIME=y
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CONFIG_LITEX_SOC_CONTROLLER=y
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CONFIG_SERIAL_LITEUART=y
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CONFIG_SERIAL_LITEUART_CONSOLE=y
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CONFIG_SOFTLOCKUP_DETECTOR=y
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CONFIG_TTY_PRINTK=y

‎arch/openrisc/include/asm/Kbuild‎

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# SPDX-License-Identifier: GPL-2.0
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generic-y += extable.h
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generic-y += kvm_para.h
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generic-y += local64.h
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generic-y += mcs_spinlock.h
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generic-y += qspinlock_types.h
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generic-y += qspinlock.h

‎arch/openrisc/kernel/traps.c‎

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asmlinkage void do_trap(struct pt_regs *regs, unsigned long address)
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{
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force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)address);
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regs->pc += 4;
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force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->pc);
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}
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asmlinkage void do_unaligned_access(struct pt_regs *regs, unsigned long address)

‎drivers/soc/Kconfig‎

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source "drivers/soc/fsl/Kconfig"
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source "drivers/soc/imx/Kconfig"
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source "drivers/soc/ixp4xx/Kconfig"
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source "drivers/soc/litex/Kconfig"
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source "drivers/soc/mediatek/Kconfig"
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source "drivers/soc/qcom/Kconfig"
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source "drivers/soc/renesas/Kconfig"

‎drivers/soc/Makefile‎

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obj-y += imx/
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obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/
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obj-$(CONFIG_SOC_XWAY) += lantiq/
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obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/
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obj-y += mediatek/
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obj-y += amlogic/
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obj-y += qcom/

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