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Abhinav Kumarlumag
Abhinav Kumar
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lumag
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drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and feature flag information. Each display compression engine (DCE) contains dual DSC encoders so both share same base address but with its own different sub block address. changes in v4: -- delete DPU_DSC_HW_REV_1_1 -- re arrange sc8280xp_dsc[] changes in v4: -- fix checkpatch warning changes in v10: -- remove hard slice from commit text -- replace DPU_DSC_NATIVE_422_EN with DPU_DSC_NATIVE_42x_EN -- change DSC_BLK_1_2 .len from 0x100 to 0x29c changes in v11: -- remove comment at DSC_BLK_1_2 marco Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/539507/ Link: https://lore.kernel.org/r/1685036458-22683-10-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
1 parent 8c4094b commit 0d1b10c

6 files changed

Lines changed: 84 additions & 1 deletion

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‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -153,6 +153,18 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
153153
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
154154
};
155155

156+
/*
157+
* NOTE: Each display compression engine (DCE) contains dual hard
158+
* slice DSC encoders so both share same base address but with
159+
* its own different sub block address.
160+
*/
161+
static const struct dpu_dsc_cfg sm8350_dsc[] = {
162+
DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
163+
DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
164+
DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
165+
DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
166+
};
167+
156168
static const struct dpu_intf_cfg sm8350_intf[] = {
157169
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
158170
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
@@ -215,6 +227,8 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
215227
.dspp = sm8350_dspp,
216228
.pingpong_count = ARRAY_SIZE(sm8350_pp),
217229
.pingpong = sm8350_pp,
230+
.dsc_count = ARRAY_SIZE(sm8350_dsc),
231+
.dsc = sm8350_dsc,
218232
.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
219233
.merge_3d = sm8350_merge_3d,
220234
.intf_count = ARRAY_SIZE(sm8350_intf),

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,11 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
9494
PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
9595
};
9696

97+
/* NOTE: sc7280 only has one DSC hard slice encoder */
98+
static const struct dpu_dsc_cfg sc7280_dsc[] = {
99+
DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
100+
};
101+
97102
static const struct dpu_wb_cfg sc7280_wb[] = {
98103
WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
99104
VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
@@ -155,6 +160,8 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {
155160
.mixer = sc7280_lm,
156161
.pingpong_count = ARRAY_SIZE(sc7280_pp),
157162
.pingpong = sc7280_pp,
163+
.dsc_count = ARRAY_SIZE(sc7280_dsc),
164+
.dsc = sc7280_dsc,
158165
.wb_count = ARRAY_SIZE(sc7280_wb),
159166
.wb = sc7280_wb,
160167
.intf_count = ARRAY_SIZE(sc7280_intf),

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,20 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
142142
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
143143
};
144144

145+
/*
146+
* NOTE: Each display compression engine (DCE) contains dual hard
147+
* slice DSC encoders so both share same base address but with
148+
* its own different sub block address.
149+
*/
150+
static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
151+
DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
152+
DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
153+
DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
154+
DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
155+
DSC_BLK_1_2("dce_2_0", DSC_4, 0x82000, 0x29c, 0, dsc_sblk_0),
156+
DSC_BLK_1_2("dce_2_1", DSC_5, 0x82000, 0x29c, 0, dsc_sblk_1),
157+
};
158+
145159
/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
146160
static const struct dpu_intf_cfg sc8280xp_intf[] = {
147161
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
@@ -217,6 +231,8 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
217231
.dspp = sc8280xp_dspp,
218232
.pingpong_count = ARRAY_SIZE(sc8280xp_pp),
219233
.pingpong = sc8280xp_pp,
234+
.dsc_count = ARRAY_SIZE(sc8280xp_dsc),
235+
.dsc = sc8280xp_dsc,
220236
.merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d),
221237
.merge_3d = sc8280xp_merge_3d,
222238
.intf_count = ARRAY_SIZE(sc8280xp_intf),

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -161,6 +161,18 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
161161
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
162162
};
163163

164+
/*
165+
* NOTE: Each display compression engine (DCE) contains dual hard
166+
* slice DSC encoders so both share same base address but with
167+
* its own different sub block address.
168+
*/
169+
static const struct dpu_dsc_cfg sm8450_dsc[] = {
170+
DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
171+
DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
172+
DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
173+
DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
174+
};
175+
164176
static const struct dpu_intf_cfg sm8450_intf[] = {
165177
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
166178
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
@@ -223,6 +235,8 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
223235
.dspp = sm8450_dspp,
224236
.pingpong_count = ARRAY_SIZE(sm8450_pp),
225237
.pingpong = sm8450_pp,
238+
.dsc_count = ARRAY_SIZE(sm8450_dsc),
239+
.dsc = sm8450_dsc,
226240
.merge_3d_count = ARRAY_SIZE(sm8450_merge_3d),
227241
.merge_3d = sm8450_merge_3d,
228242
.intf_count = ARRAY_SIZE(sm8450_intf),

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -165,6 +165,18 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
165165
MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700),
166166
};
167167

168+
/*
169+
* NOTE: Each display compression engine (DCE) contains dual hard
170+
* slice DSC encoders so both share same base address but with
171+
* its own different sub block address.
172+
*/
173+
static const struct dpu_dsc_cfg sm8550_dsc[] = {
174+
DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0),
175+
DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1),
176+
DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0),
177+
DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1),
178+
};
179+
168180
static const struct dpu_intf_cfg sm8550_intf[] = {
169181
INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
170182
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
@@ -227,6 +239,8 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
227239
.dspp = sm8550_dspp,
228240
.pingpong_count = ARRAY_SIZE(sm8550_pp),
229241
.pingpong = sm8550_pp,
242+
.dsc_count = ARRAY_SIZE(sm8550_dsc),
243+
.dsc = sm8550_dsc,
230244
.merge_3d_count = ARRAY_SIZE(sm8550_merge_3d),
231245
.merge_3d = sm8550_merge_3d,
232246
.intf_count = ARRAY_SIZE(sm8550_intf),

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c‎

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// SPDX-License-Identifier: GPL-2.0-only
22
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3-
* Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
3+
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
44
*/
55

66
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
@@ -516,13 +516,31 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
516516
/*************************************************************
517517
* DSC sub blocks config
518518
*************************************************************/
519+
static const struct dpu_dsc_sub_blks dsc_sblk_0 = {
520+
.enc = {.base = 0x100, .len = 0x100},
521+
.ctl = {.base = 0xF00, .len = 0x10},
522+
};
523+
524+
static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
525+
.enc = {.base = 0x200, .len = 0x100},
526+
.ctl = {.base = 0xF80, .len = 0x10},
527+
};
528+
519529
#define DSC_BLK(_name, _id, _base, _features) \
520530
{\
521531
.name = _name, .id = _id, \
522532
.base = _base, .len = 0x140, \
523533
.features = _features, \
524534
}
525535

536+
#define DSC_BLK_1_2(_name, _id, _base, _len, _features, _sblk) \
537+
{\
538+
.name = _name, .id = _id, \
539+
.base = _base, .len = _len, \
540+
.features = BIT(DPU_DSC_HW_REV_1_2) | _features, \
541+
.sblk = &_sblk, \
542+
}
543+
526544
/*************************************************************
527545
* INTF sub blocks config
528546
*************************************************************/

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